llvm-6502/test/CodeGen/ARM64/fast-isel-rem.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

34 lines
636 B
LLVM

; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
define i32 @t1(i32 %a, i32 %b) {
; CHECK: @t1
; CHECK: sdiv w2, w0, w1
; CHECK: msub w2, w2, w1, w0
%1 = srem i32 %a, %b
ret i32 %1
}
define i64 @t2(i64 %a, i64 %b) {
; CHECK: @t2
; CHECK: sdiv x2, x0, x1
; CHECK: msub x2, x2, x1, x0
%1 = srem i64 %a, %b
ret i64 %1
}
define i32 @t3(i32 %a, i32 %b) {
; CHECK: @t3
; CHECK: udiv w2, w0, w1
; CHECK: msub w2, w2, w1, w0
%1 = urem i32 %a, %b
ret i32 %1
}
define i64 @t4(i64 %a, i64 %b) {
; CHECK: @t4
; CHECK: udiv x2, x0, x1
; CHECK: msub x2, x2, x1, x0
%1 = urem i64 %a, %b
ret i64 %1
}