mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
34 lines
731 B
LLVM
34 lines
731 B
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
|
|
|
|
define zeroext i8 @f1(<16 x i8> %a) {
|
|
; CHECK-LABEL: f1:
|
|
; CHECK: umov.b w0, v0[3]
|
|
; CHECK-NEXT: ret
|
|
%vecext = extractelement <16 x i8> %a, i32 3
|
|
ret i8 %vecext
|
|
}
|
|
|
|
define zeroext i16 @f2(<4 x i16> %a) {
|
|
; CHECK-LABEL: f2:
|
|
; CHECK: umov.h w0, v0[2]
|
|
; CHECK-NEXT: ret
|
|
%vecext = extractelement <4 x i16> %a, i32 2
|
|
ret i16 %vecext
|
|
}
|
|
|
|
define i32 @f3(<2 x i32> %a) {
|
|
; CHECK-LABEL: f3:
|
|
; CHECK: umov.s w0, v0[1]
|
|
; CHECK-NEXT: ret
|
|
%vecext = extractelement <2 x i32> %a, i32 1
|
|
ret i32 %vecext
|
|
}
|
|
|
|
define i64 @f4(<2 x i64> %a) {
|
|
; CHECK-LABEL: f4:
|
|
; CHECK: umov.d x0, v0[1]
|
|
; CHECK-NEXT: ret
|
|
%vecext = extractelement <2 x i64> %a, i32 1
|
|
ret i64 %vecext
|
|
}
|