Andrew Lenharth 3b628f8388 this pattern was bogus ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25197 91177308-0d34-0410-b5e6-96231b3b80d8		2006-01-11 03:33:06 +00:00
..
.cvsignore
Alpha.h
Alpha.td
AlphaAsmPrinter.cpp	add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG	2005-12-25 17:36:48 +00:00
AlphaCodeEmitter.cpp	massive DAGISel patch. lots and lots more stuff compiles now	2005-11-22 04:20:06 +00:00
AlphaInstrFormats.td	Move brcond over and fix some imm patterns. This may be the last change before changing the default alpha isel.	2006-01-01 22:16:14 +00:00
AlphaInstrInfo.cpp
AlphaInstrInfo.h
AlphaInstrInfo.td	this pattern was bogus	2006-01-11 03:33:06 +00:00
AlphaISelDAGToDAG.cpp	make 0 codegen much better	2006-01-06 19:41:51 +00:00
AlphaISelLowering.cpp	Had expand logic backward.	2006-01-05 01:47:43 +00:00
AlphaISelLowering.h	All that just to lower div and rem	2005-12-25 01:34:27 +00:00
AlphaISelPattern.cpp	add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG	2005-12-25 17:36:48 +00:00
AlphaJITInfo.cpp	Remove a 'using namespace std'.	2006-01-01 22:20:31 +00:00
AlphaJITInfo.h
AlphaRegisterInfo.cpp	clean this function up some	2006-01-01 22:13:54 +00:00
AlphaRegisterInfo.h
AlphaRegisterInfo.td	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
AlphaRelocations.h
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetMachine.cpp
AlphaTargetMachine.h
Makefile