mirror of
https://github.com/c64scene-ar/llvm-6502.git
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c6c7e85a71
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144212 91177308-0d34-0410-b5e6-96231b3b80d8
129 lines
3.1 KiB
LLVM
129 lines
3.1 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
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; CHECK: vpandn
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; CHECK: vpandn %ymm
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; CHECK: ret
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define <4 x i64> @vpandn(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%y = xor <4 x i64> %a2, <i64 -1, i64 -1, i64 -1, i64 -1>
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%x = and <4 x i64> %a, %y
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ret <4 x i64> %x
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}
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; CHECK: vpand
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; CHECK: vpand %ymm
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; CHECK: ret
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define <4 x i64> @vpand(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = and <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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; CHECK: vpor
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; CHECK: vpor %ymm
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; CHECK: ret
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define <4 x i64> @vpor(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = or <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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; CHECK: vpxor
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; CHECK: vpxor %ymm
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; CHECK: ret
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define <4 x i64> @vpxor(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = xor <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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; CHECK: vpblendvb
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; CHECK: vpblendvb %ymm
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; CHECK: ret
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define <32 x i8> @vpblendvb(<32 x i8> %x, <32 x i8> %y) {
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%min_is_x = icmp ult <32 x i8> %x, %y
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%min = select <32 x i1> %min_is_x, <32 x i8> %x, <32 x i8> %y
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ret <32 x i8> %min
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}
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; CHECK: variable_shl0
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; CHECK: psllvd
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; CHECK: ret
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define <4 x i32> @variable_shl0(<4 x i32> %x, <4 x i32> %y) {
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%k = shl <4 x i32> %x, %y
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ret <4 x i32> %k
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}
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; CHECK: variable_shl1
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; CHECK: psllvd
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; CHECK: ret
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define <8 x i32> @variable_shl1(<8 x i32> %x, <8 x i32> %y) {
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%k = shl <8 x i32> %x, %y
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ret <8 x i32> %k
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}
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; CHECK: variable_shl2
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; CHECK: psllvq
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; CHECK: ret
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define <2 x i64> @variable_shl2(<2 x i64> %x, <2 x i64> %y) {
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%k = shl <2 x i64> %x, %y
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ret <2 x i64> %k
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}
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; CHECK: variable_shl3
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; CHECK: psllvq
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; CHECK: ret
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define <4 x i64> @variable_shl3(<4 x i64> %x, <4 x i64> %y) {
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%k = shl <4 x i64> %x, %y
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ret <4 x i64> %k
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}
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; CHECK: variable_srl0
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; CHECK: psrlvd
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; CHECK: ret
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define <4 x i32> @variable_srl0(<4 x i32> %x, <4 x i32> %y) {
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%k = lshr <4 x i32> %x, %y
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ret <4 x i32> %k
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}
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; CHECK: variable_srl1
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; CHECK: psrlvd
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; CHECK: ret
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define <8 x i32> @variable_srl1(<8 x i32> %x, <8 x i32> %y) {
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%k = lshr <8 x i32> %x, %y
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ret <8 x i32> %k
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}
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; CHECK: variable_srl2
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; CHECK: psrlvq
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; CHECK: ret
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define <2 x i64> @variable_srl2(<2 x i64> %x, <2 x i64> %y) {
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%k = lshr <2 x i64> %x, %y
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ret <2 x i64> %k
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}
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; CHECK: variable_srl3
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; CHECK: psrlvq
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; CHECK: ret
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define <4 x i64> @variable_srl3(<4 x i64> %x, <4 x i64> %y) {
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%k = lshr <4 x i64> %x, %y
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ret <4 x i64> %k
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}
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; CHECK: variable_sra0
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; CHECK: psravd
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; CHECK: ret
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define <4 x i32> @variable_sra0(<4 x i32> %x, <4 x i32> %y) {
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%k = ashr <4 x i32> %x, %y
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ret <4 x i32> %k
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}
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; CHECK: variable_sra1
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; CHECK: psravd
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; CHECK: ret
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define <8 x i32> @variable_sra1(<8 x i32> %x, <8 x i32> %y) {
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%k = ashr <8 x i32> %x, %y
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ret <8 x i32> %k
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}
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