llvm-6502/test/CodeGen
Benjamin Kramer 6242fda42a DAGCombiner: Canonicalize vector integer abs in the same way we do it for scalars.
This already helps SSE2 x86 a lot because it lacks an efficient way to
represent a vector select. The long term goal is to enable the backend to match
a canonicalized pattern into a single instruction (e.g. vabs or pabs).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180597 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 09:19:19 +00:00
..
AArch64
ARM Fix constant folding for one lane vector types. Constant folding one lane vector types not returns a vector instead of a scalar. 2013-04-25 09:32:33 +00:00
CPP
Generic
Hexagon Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. 2013-04-23 21:17:40 +00:00
Inputs
MBlaze
Mips
MSP430
NVPTX
PowerPC
R600 R600: Use SHT_PROGBITS for the .AMDGPU.config section 2013-04-24 23:56:14 +00:00
SI
SPARC
Thumb
Thumb2
X86 DAGCombiner: Canonicalize vector integer abs in the same way we do it for scalars. 2013-04-26 09:19:19 +00:00
XCore