Matt Arsenault 1bd96c574c R600/SI: Implement areMemAccessesTriviallyDisjoint ... This partially makes up for not having address spaces used for alias analysis in some simple cases. This is not yet enabled by default so shouldn't change anything yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222286 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-19 00:01:31 +00:00
..
AArch64	[FastISel][AArch64] Also allow folding of sign-/zero-extend and arithmetic	2014-11-18 22:41:49 +00:00
ARM	Fix ARM triple parsing	2014-11-17 14:08:57 +00:00
CPP
Generic
Hexagon
Inputs
Mips	First stage of call lowering for Mips fast-isel	2014-11-13 23:37:45 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add VSX builtins for vec_div	2014-11-14 12:10:40 +00:00
R600	R600/SI: Implement areMemAccessesTriviallyDisjoint	2014-11-19 00:01:31 +00:00
SPARC
SystemZ
Thumb	[Thumb1] Re-write emitThumbRegPlusImmediate	2014-11-17 11:18:10 +00:00
Thumb2	ARM: allow constpool entry to be moved to the user's block in all cases.	2014-11-13 17:58:53 +00:00
X86	[X86][AVX] 256-bit vector stack unaligned load/stores identification	2014-11-18 23:38:19 +00:00
XCore