llvm-6502/lib/Target/PowerPC
2006-01-14 01:24:22 +00:00
..
.cvsignore ignore generated files. 2004-11-21 00:00:54 +00:00
LICENSE.TXT Added Louis Gerbarg. Louis is given credit in the CREDITS.TXT file, so I 2004-08-05 23:46:27 +00:00
Makefile Plugin new subtarget backend into the build. 2005-10-21 19:05:19 +00:00
PPC.h Goodbye PPC pattern isel. You have served us well, but it is now time for 2006-01-12 01:46:07 +00:00
PPC.td Add attribute name and type to SubtargetFeatures. 2005-10-26 17:28:23 +00:00
PPCAsmPrinter.cpp Added initial support for DEBUG_LABEL allowing debug specific labels to be 2006-01-05 01:25:28 +00:00
PPCBranchSelector.cpp More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCCodeEmitter.cpp Fix the PPC JIT failures last night, which were due to mishandling of linkonce globals 2006-01-07 06:22:16 +00:00
PPCFrameInfo.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCInstrBuilder.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCInstrFormats.td Pattern-match return. Includes gross hack! 2005-12-20 00:26:01 +00:00
PPCInstrInfo.cpp teach ppc backend these are copies 2005-10-19 01:50:36 +00:00
PPCInstrInfo.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCInstrInfo.td ahem :) 2006-01-12 02:05:36 +00:00
PPCISelDAGToDAG.cpp these cases are autogenerated 2006-01-12 02:01:45 +00:00
PPCISelLowering.cpp implement stacksave/stackrestore on PPC 2006-01-13 17:52:03 +00:00
PPCISelLowering.h Give PPCISD:: nodes legible names in dumps. 2006-01-09 23:52:17 +00:00
PPCJITInfo.cpp More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCJITInfo.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCRegisterInfo.cpp Fix an off-by-one error that Nate's eagle eyes caught 2006-01-11 23:16:29 +00:00
PPCRegisterInfo.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCRegisterInfo.td Bye bye HACKTROCITY. 2005-12-22 02:26:21 +00:00
PPCRelocations.h More PPC32 -> PPC changes, as well as merging some classes that were 2005-10-16 05:39:50 +00:00
PPCSchedule.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCScheduleG3.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCScheduleG4.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCScheduleG4Plus.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCScheduleG5.td Added InstrSchedClass to each of the PowerPC Instructions. 2005-10-19 19:51:16 +00:00
PPCSubtarget.cpp add an option to generate completely non-pic code, corresponding to what 2005-11-17 18:55:48 +00:00
PPCSubtarget.h Allow itineraries to be passed through the Target Machine. 2005-11-01 20:06:59 +00:00
PPCTargetMachine.cpp Goodbye PPC pattern isel. You have served us well, but it is now time for 2006-01-12 01:46:07 +00:00
PPCTargetMachine.h Add a new option to indicate we want the code generator to emit code quickly, 2005-11-08 02:12:47 +00:00
README.txt Remove some redundant stuff out of the readme. 2006-01-14 01:24:22 +00:00

TODO:
* gpr0 allocation
* implement do-loop -> bdnz transform
* implement powerpc-64 for darwin
* use stfiwx in float->int

* Fold add and sub with constant into non-extern, non-weak addresses so this:
	lis r2, ha16(l2__ZTV4Cell)
	la r2, lo16(l2__ZTV4Cell)(r2)
	addi r2, r2, 8
becomes:
	lis r2, ha16(l2__ZTV4Cell+8)
	la r2, lo16(l2__ZTV4Cell+8)(r2)


* Teach LLVM how to codegen this:
unsigned short foo(float a) { return a; }
as:
_foo:
        fctiwz f0,f1
        stfd f0,-8(r1)
        lhz r3,-2(r1)
        blr
not:
_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr

* Support 'update' load/store instructions.  These are cracked on the G5, but
  are still a codesize win.

* should hint to the branch select pass that it doesn't need to print the
  second unconditional branch, so we don't end up with things like:
	b .LBBl42__2E_expand_function_8_674	; loopentry.24
	b .LBBl42__2E_expand_function_8_42	; NewDefault
	b .LBBl42__2E_expand_function_8_42	; NewDefault

===-------------------------------------------------------------------------===

* Codegen this:

   void test2(int X) {
     if (X == 0x12345678) bar();
   }

    as:

       xoris r0,r3,0x1234
       cmpwi cr0,r0,0x5678
       beq cr0,L6

    not:

        lis r2, 4660
        ori r2, r2, 22136 
        cmpw cr0, r3, r2  
        bne .LBB_test2_2

===-------------------------------------------------------------------------===

Lump the constant pool for each function into ONE pic object, and reference
pieces of it as offsets from the start.  For functions like this (contrived
to have lots of constants obviously):

double X(double Y) { return (Y*1.23 + 4.512)*2.34 + 14.38; }

We generate:

_X:
        lis r2, ha16(.CPI_X_0)
        lfd f0, lo16(.CPI_X_0)(r2)
        lis r2, ha16(.CPI_X_1)
        lfd f2, lo16(.CPI_X_1)(r2)
        fmadd f0, f1, f0, f2
        lis r2, ha16(.CPI_X_2)
        lfd f1, lo16(.CPI_X_2)(r2)
        lis r2, ha16(.CPI_X_3)
        lfd f2, lo16(.CPI_X_3)(r2)
        fmadd f1, f0, f1, f2
        blr

It would be better to materialize .CPI_X into a register, then use immediates
off of the register to avoid the lis's.  This is even more important in PIC 
mode.

===-------------------------------------------------------------------------===

Implement Newton-Rhapson method for improving estimate instructions to the
correct accuracy, and implementing divide as multiply by reciprocal when it has
more than one use.  Itanium will want this too.

===-------------------------------------------------------------------------===

int foo(int a, int b) { return a == b ? 16 : 0; }
_foo:
        cmpw cr7, r3, r4
        mfcr r2
        rlwinm r2, r2, 31, 31, 31
        slwi r3, r2, 4
        blr

If we exposed the srl & mask ops after the MFCR that we are doing to select
the correct CR bit, then we could fold the slwi into the rlwinm before it.

===-------------------------------------------------------------------------===

#define  ARRAY_LENGTH  16

union bitfield {
	struct {
#ifndef	__ppc__
		unsigned int                       field0 : 6;
		unsigned int                       field1 : 6;
		unsigned int                       field2 : 6;
		unsigned int                       field3 : 6;
		unsigned int                       field4 : 3;
		unsigned int                       field5 : 4;
		unsigned int                       field6 : 1;
#else
		unsigned int                       field6 : 1;
		unsigned int                       field5 : 4;
		unsigned int                       field4 : 3;
		unsigned int                       field3 : 6;
		unsigned int                       field2 : 6;
		unsigned int                       field1 : 6;
		unsigned int                       field0 : 6;
#endif
	} bitfields, bits;
	unsigned int	u32All;
	signed int	i32All;
	float	f32All;
};


typedef struct program_t {
	union bitfield    array[ARRAY_LENGTH];
    int               size;
    int               loaded;
} program;


void AdjustBitfields(program* prog, unsigned int fmt1)
{
	unsigned int shift = 0;
	unsigned int texCount = 0;
	unsigned int i;
	
	for (i = 0; i < 8; i++)
	{
		prog->array[i].bitfields.field0 = texCount;
		prog->array[i].bitfields.field1 = texCount + 1;
		prog->array[i].bitfields.field2 = texCount + 2;
		prog->array[i].bitfields.field3 = texCount + 3;

		texCount += (fmt1 >> shift) & 0x7;
		shift    += 3;
	}
}

In the loop above, the bitfield adds get generated as 
(add (shl bitfield, C1), (shl C2, C1)) where C2 is 1, 2 or 3.

Since the input to the (or and, and) is an (add) rather than a (shl), the shift
doesn't get folded into the rlwimi instruction.  We should ideally see through
things like this, rather than forcing llvm to generate the equivalent

(shl (add bitfield, C2), C1) with some kind of mask.

===-------------------------------------------------------------------------===

Compile this:

int %f1(int %a, int %b) {
        %tmp.1 = and int %a, 15         ; <int> [#uses=1]
        %tmp.3 = and int %b, 240                ; <int> [#uses=1]
        %tmp.4 = or int %tmp.3, %tmp.1          ; <int> [#uses=1]
        ret int %tmp.4
}

without a copy.  We make this currently:

_f1:
        rlwinm r2, r4, 0, 24, 27
        rlwimi r2, r3, 0, 28, 31
        or r3, r2, r2
        blr

The two-addr pass or RA needs to learn when it is profitable to commute an
instruction to avoid a copy AFTER the 2-addr instruction.  The 2-addr pass
currently only commutes to avoid inserting a copy BEFORE the two addr instr.

===-------------------------------------------------------------------------===

Compile offsets from allocas:

int *%test() {
        %X = alloca { int, int }
        %Y = getelementptr {int,int}* %X, int 0, uint 1
        ret int* %Y
}

into a single add, not two:

_test:
        addi r2, r1, -8
        addi r3, r2, 4
        blr

--> important for C++.

===-------------------------------------------------------------------------===

int test3(int a, int b) { return (a < 0) ? a : 0; }

should be branch free code.  LLVM is turning it into < 1 because of the RHS.

===-------------------------------------------------------------------------===

No loads or stores of the constants should be needed:

struct foo { double X, Y; };
void xxx(struct foo F);
void bar() { struct foo R = { 1.0, 2.0 }; xxx(R); }