mirror of
https://github.com/c64scene-ar/llvm-6502.git
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85dc7da6f3
This partially fixes weird looking load scheduling in memcpy test. The load clustering doesn't seem particularly smart, but this method seems to be partially deprecated so it might not be worth trying to fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214943 91177308-0d34-0410-b5e6-96231b3b80d8
364 lines
12 KiB
C++
364 lines
12 KiB
C++
//===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Implementation of the TargetInstrInfo class that is common to all
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/// AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#define GET_INSTRINFO_NAMED_OPS
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#define GET_INSTRMAP_INFO
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#include "AMDGPUGenInstrInfo.inc"
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// Pin the vtable to this file.
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void AMDGPUInstrInfo::anchor() {}
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AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &st)
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: AMDGPUGenInstrInfo(-1,-1), RI(st), ST(st) { }
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const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
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return RI;
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}
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bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const {
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// TODO: Implement this function
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return false;
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}
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unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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// TODO: Implement this function
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return 0;
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}
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unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const {
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// TODO: Implement this function
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return 0;
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}
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bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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// TODO: Implement this function
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return false;
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}
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unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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// TODO: Implement this function
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return 0;
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}
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unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const {
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// TODO: Implement this function
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return 0;
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}
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bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,
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const MachineMemOperand *&MMO,
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int &FrameIndex) const {
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// TODO: Implement this function
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return false;
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}
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MachineInstr *
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AMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const {
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// TODO: Implement this function
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return nullptr;
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}
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bool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter,
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MachineBasicBlock &MBB) const {
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while (iter != MBB.end()) {
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switch (iter->getOpcode()) {
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default:
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break;
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case AMDGPU::BRANCH_COND_i32:
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case AMDGPU::BRANCH_COND_f32:
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case AMDGPU::BRANCH:
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return true;
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};
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++iter;
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}
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return false;
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}
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void
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AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill,
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int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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llvm_unreachable("Not Implemented");
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}
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void
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AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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llvm_unreachable("Not Implemented");
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}
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bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
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MachineBasicBlock *MBB = MI->getParent();
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int OffsetOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::addr);
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// addr is a custom operand with multiple MI operands, and only the
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// first MI operand is given a name.
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int RegOpIdx = OffsetOpIdx + 1;
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int ChanOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::chan);
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if (isRegisterLoad(*MI)) {
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int DstOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::dst);
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unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
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unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
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unsigned Address = calculateIndirectAddress(RegIndex, Channel);
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unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
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if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
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buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
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getIndirectAddrRegClass()->getRegister(Address));
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} else {
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buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
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Address, OffsetReg);
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}
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} else if (isRegisterStore(*MI)) {
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int ValOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::val);
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unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
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unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
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unsigned Address = calculateIndirectAddress(RegIndex, Channel);
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unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
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if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
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buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
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MI->getOperand(ValOpIdx).getReg());
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} else {
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buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg(),
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calculateIndirectAddress(RegIndex, Channel),
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OffsetReg);
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}
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} else {
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return false;
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}
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MBB->erase(MI);
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return true;
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}
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MachineInstr *
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AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const {
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// TODO: Implement this function
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return nullptr;
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}
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MachineInstr*
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AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr *LoadMI) const {
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// TODO: Implement this function
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return nullptr;
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}
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bool
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AMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const {
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// TODO: Implement this function
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return false;
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}
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bool
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AMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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unsigned Reg, bool UnfoldLoad,
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bool UnfoldStore,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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// TODO: Implement this function
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return false;
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}
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bool
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AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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SmallVectorImpl<SDNode*> &NewNodes) const {
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// TODO: Implement this function
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return false;
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}
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unsigned
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AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
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bool UnfoldLoad, bool UnfoldStore,
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unsigned *LoadRegIndex) const {
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// TODO: Implement this function
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return 0;
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}
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bool AMDGPUInstrInfo::enableClusterLoads() const {
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return true;
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}
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// FIXME: This behaves strangely. If, for example, you have 32 load + stores,
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// the first 16 loads will be interleaved with the stores, and the next 16 will
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// be clustered as expected. It should really split into 2 16 store batches.
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//
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// Loads are clustered until this returns false, rather than trying to schedule
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// groups of stores. This also means we have to deal with saying different
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// address space loads should be clustered, and ones which might cause bank
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// conflicts.
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//
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// This might be deprecated so it might not be worth that much effort to fix.
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bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,
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int64_t Offset0, int64_t Offset1,
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unsigned NumLoads) const {
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assert(Offset1 > Offset0 &&
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"Second offset should be larger than first offset!");
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// If we have less than 16 loads in a row, and the offsets are within 64
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// bytes, then schedule together.
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// A cacheline is 64 bytes (for global memory).
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return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
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}
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bool
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AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
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const {
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// TODO: Implement this function
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return true;
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}
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void AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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// TODO: Implement this function
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}
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bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {
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// TODO: Implement this function
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return false;
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}
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bool
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AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2)
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const {
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// TODO: Implement this function
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return false;
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}
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bool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const {
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// TODO: Implement this function
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return false;
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}
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bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {
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// TODO: Implement this function
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return MI->getDesc().isPredicable();
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}
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bool
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AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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// TODO: Implement this function
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return true;
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}
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bool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const {
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return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
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}
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bool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const {
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return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
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}
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int AMDGPUInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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int Offset = -1;
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if (MFI->getNumObjects() == 0) {
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return -1;
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}
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if (MRI.livein_empty()) {
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return 0;
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}
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const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
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for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
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LE = MRI.livein_end();
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LI != LE; ++LI) {
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unsigned Reg = LI->first;
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if (TargetRegisterInfo::isVirtualRegister(Reg) ||
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!IndirectRC->contains(Reg))
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continue;
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unsigned RegIndex;
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unsigned RegEnd;
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for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
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++RegIndex) {
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if (IndirectRC->getRegister(RegIndex) == Reg)
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break;
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}
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Offset = std::max(Offset, (int)RegIndex);
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}
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return Offset + 1;
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}
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int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
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int Offset = 0;
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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// Variable sized objects are not supported
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assert(!MFI->hasVarSizedObjects());
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if (MFI->getNumObjects() == 0) {
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return -1;
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}
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Offset = MF.getTarget()
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.getSubtargetImpl()
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->getFrameLowering()
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->getFrameIndexOffset(MF, -1);
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return getIndirectIndexBegin(MF) + Offset;
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}
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int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
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switch (Channels) {
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default: return Opcode;
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case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
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case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
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case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
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}
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}
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// Wrapper for Tablegen'd function. enum Subtarget is not defined in any
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// header files, so we need to wrap it in a function that takes unsigned
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// instead.
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namespace llvm {
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namespace AMDGPU {
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int getMCOpcode(uint16_t Opcode, unsigned Gen) {
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return getMCOpcode(Opcode);
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}
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}
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}
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