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e8be6c6391
replacement of multiple values. This is slightly more efficient than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically could be optimized even further. However, an important property of this new function is that it handles the case where the source value set and destination value set overlap. This makes it feasible for isel to use SelectNodeTo in many very common cases, which is advantageous because SelectNodeTo avoids a temporary node and it doesn't require CSEMap updates for users of values that don't change position. Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to handle operand lists more efficiently, and to correctly handle a number of corner cases to which its new wider use exposes it. This commit also includes a change to the encoding of post-isel opcodes in SDNodes; now instead of being sandwiched between the target-independent pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel opcodes are now represented as negative values. This makes it possible to test if an opcode is pre-isel or post-isel without having to know the size of the current target's post-isel instruction set. These changes speed up llc overall by 3% and reduce memory usage by 10% on the InstructionCombining.cpp testcase with -fast and -regalloc=local. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| .. | ||
| IA64.h | ||
| IA64.td | ||
| IA64AsmPrinter.cpp | ||
| IA64Bundling.cpp | ||
| IA64InstrBuilder.h | ||
| IA64InstrFormats.td | ||
| IA64InstrInfo.cpp | ||
| IA64InstrInfo.h | ||
| IA64InstrInfo.td | ||
| IA64ISelDAGToDAG.cpp | ||
| IA64ISelLowering.cpp | ||
| IA64ISelLowering.h | ||
| IA64MachineFunctionInfo.h | ||
| IA64RegisterInfo.cpp | ||
| IA64RegisterInfo.h | ||
| IA64RegisterInfo.td | ||
| IA64TargetAsmInfo.cpp | ||
| IA64TargetAsmInfo.h | ||
| IA64TargetMachine.cpp | ||
| IA64TargetMachine.h | ||
| Makefile | ||
| README | ||
TODO:
- Un-bitrot ISel
- Hook up If-Conversion a la ARM target
- Hook up all branch analysis functions
- Instruction scheduling
- Bundling
- Dynamic Optimization
- Testing and bugfixing
- stop passing FP args in both FP *and* integer regs when not required
- allocate low (nonstacked) registers more aggressively
- clean up and thoroughly test the isel patterns.
- fix stacked register allocation order: (for readability) we don't want
the out? registers being the first ones used
- fix up floating point
(nb http://gcc.gnu.org/wiki?pagename=ia64%20floating%20point )
- bundling!
(we will avoid the mess that is:
http://gcc.gnu.org/ml/gcc/2003-12/msg00832.html )
- instruction scheduling (hmmmm! ;)
- counted loop support
- make integer + FP mul/div more clever (we have fixed pseudocode atm)
- track and use comparison complements
INFO:
- we are strictly LP64 here, no support for ILP32 on HP-UX. Linux users
don't need to worry about this.
- i have instruction scheduling/bundling pseudocode, that really works
(has been tested, albeit at the perl-script level).
so, before you go write your own, send me an email!
KNOWN DEFECTS AT THE CURRENT TIME:
- C++ vtables contain naked function pointers, not function descriptors,
which is bad. see http://llvm.cs.uiuc.edu/bugs/show_bug.cgi?id=406
- varargs are broken
- alloca doesn't work (indeed, stack frame layout is bogus)
- no support for big-endian environments
- (not really the backend, but...) the CFE has some issues on IA64.
these will probably be fixed soon.
ACKNOWLEDGEMENTS:
- Chris Lattner (x100)
- Other LLVM developers ("hey, that looks familiar")
CONTACT:
- You can email me at duraid@octopus.com.au. If you find a small bug,
just email me. If you find a big bug, please file a bug report
in bugzilla! http://llvm.cs.uiuc.edu is your one stop shop for all
things LLVM.