mirror of
https://github.com/c64scene-ar/llvm-6502.git
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62d66cbec5
Patch by Cameron McInally <cameron.mcinally@nyu.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193497 91177308-0d34-0410-b5e6-96231b3b80d8
292 lines
11 KiB
LLVM
292 lines
11 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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declare i32 @llvm.x86.avx512.kortestz(i16, i16) nounwind readnone
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; CHECK: test_kortestz
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; CHECK: kortestw
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; CHECK: sete
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define i32 @test_kortestz(i16 %a0, i16 %a1) {
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%res = call i32 @llvm.x86.avx512.kortestz(i16 %a0, i16 %a1)
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ret i32 %res
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}
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declare i32 @llvm.x86.avx512.kortestc(i16, i16) nounwind readnone
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; CHECK: test_kortestc
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; CHECK: kortestw
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; CHECK: sbbl
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define i32 @test_kortestc(i16 %a0, i16 %a1) {
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%res = call i32 @llvm.x86.avx512.kortestc(i16 %a0, i16 %a1)
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ret i32 %res
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}
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define <16 x float> @test_rcp_ps_512(<16 x float> %a0) {
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; CHECK: vrcp14ps
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%res = call <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float> %a0) ; <<16 x float>> [#uses=1]
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.avx512.rcp14.ps.512(<16 x float>) nounwind readnone
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define <8 x double> @test_rcp_pd_512(<8 x double> %a0) {
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; CHECK: vrcp14pd
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%res = call <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double> %a0) ; <<8 x double>> [#uses=1]
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ret <8 x double> %res
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}
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declare <8 x double> @llvm.x86.avx512.rcp14.pd.512(<8 x double>) nounwind readnone
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define <16 x float> @test_rcp28_ps_512(<16 x float> %a0) {
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; CHECK: vrcp28ps
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%res = call <16 x float> @llvm.x86.avx512.rcp28.ps.512(<16 x float> %a0) ; <<16 x float>> [#uses=1]
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.avx512.rcp28.ps.512(<16 x float>) nounwind readnone
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define <8 x double> @test_rcp28_pd_512(<8 x double> %a0) {
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; CHECK: vrcp28pd
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%res = call <8 x double> @llvm.x86.avx512.rcp28.pd.512(<8 x double> %a0) ; <<8 x double>> [#uses=1]
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ret <8 x double> %res
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}
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declare <8 x double> @llvm.x86.avx512.rcp28.pd.512(<8 x double>) nounwind readnone
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define <8 x double> @test_rndscale_pd_512(<8 x double> %a0) {
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; CHECK: vrndscale
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%res = call <8 x double> @llvm.x86.avx512.rndscale.pd.512(<8 x double> %a0, i32 7) ; <<8 x double>> [#uses=1]
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ret <8 x double> %res
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}
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declare <8 x double> @llvm.x86.avx512.rndscale.pd.512(<8 x double>, i32) nounwind readnone
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define <16 x float> @test_rndscale_ps_512(<16 x float> %a0) {
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; CHECK: vrndscale
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%res = call <16 x float> @llvm.x86.avx512.rndscale.ps.512(<16 x float> %a0, i32 7) ; <<16 x float>> [#uses=1]
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.avx512.rndscale.ps.512(<16 x float>, i32) nounwind readnone
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define <16 x float> @test_rsqrt_ps_512(<16 x float> %a0) {
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; CHECK: vrsqrt14ps
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%res = call <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float> %a0) ; <<16 x float>> [#uses=1]
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.avx512.rsqrt14.ps.512(<16 x float>) nounwind readnone
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define <16 x float> @test_rsqrt28_ps_512(<16 x float> %a0) {
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; CHECK: vrsqrt28ps
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%res = call <16 x float> @llvm.x86.avx512.rsqrt28.ps.512(<16 x float> %a0) ; <<16 x float>> [#uses=1]
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.avx512.rsqrt28.ps.512(<16 x float>) nounwind readnone
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define <4 x float> @test_rsqrt14_ss(<4 x float> %a0) {
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; CHECK: vrsqrt14ss
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%res = call <4 x float> @llvm.x86.avx512.rsqrt14.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx512.rsqrt14.ss(<4 x float>) nounwind readnone
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define <4 x float> @test_rsqrt28_ss(<4 x float> %a0) {
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; CHECK: vrsqrt28ss
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%res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float>) nounwind readnone
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define <4 x float> @test_rcp14_ss(<4 x float> %a0) {
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; CHECK: vrcp14ss
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%res = call <4 x float> @llvm.x86.avx512.rcp14.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx512.rcp14.ss(<4 x float>) nounwind readnone
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define <4 x float> @test_rcp28_ss(<4 x float> %a0) {
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; CHECK: vrcp28ss
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%res = call <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float>) nounwind readnone
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define <8 x double> @test_sqrt_pd_512(<8 x double> %a0) {
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; CHECK: vsqrtpd
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%res = call <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double> %a0) ; <<8 x double>> [#uses=1]
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ret <8 x double> %res
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}
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declare <8 x double> @llvm.x86.avx512.sqrt.pd.512(<8 x double>) nounwind readnone
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define <16 x float> @test_sqrt_ps_512(<16 x float> %a0) {
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; CHECK: vsqrtps
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%res = call <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float> %a0) ; <<16 x float>> [#uses=1]
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.avx512.sqrt.ps.512(<16 x float>) nounwind readnone
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define <4 x float> @test_sqrt_ss(<4 x float> %a0, <4 x float> %a1) {
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; CHECK: vsqrtssz
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%res = call <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx512.sqrt.ss(<4 x float>, <4 x float>) nounwind readnone
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define <2 x double> @test_sqrt_sd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK: vsqrtsdz
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%res = call <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.avx512.sqrt.sd(<2 x double>, <2 x double>) nounwind readnone
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define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) {
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; CHECK: vcvtsd2siz
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%res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
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ret i64 %res
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}
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declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
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define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) {
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; CHECK: vcvtsi2sdqz
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%res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
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define <2 x double> @test_x86_avx512_cvtusi642sd(<2 x double> %a0, i64 %a1) {
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; CHECK: vcvtusi2sdqz
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%res = call <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.avx512.cvtusi642sd(<2 x double>, i64) nounwind readnone
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define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {
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; CHECK: vcvttsd2siz
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%res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
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ret i64 %res
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}
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declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
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define i64 @test_x86_sse_cvtss2si64(<4 x float> %a0) {
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; CHECK: vcvtss2siz
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%res = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0) ; <i64> [#uses=1]
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ret i64 %res
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}
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declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_cvtsi642ss(<4 x float> %a0, i64 %a1) {
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; CHECK: vcvtsi2ssqz
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%res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone
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define i64 @test_x86_sse_cvttss2si64(<4 x float> %a0) {
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; CHECK: vcvttss2siz
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%res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0) ; <i64> [#uses=1]
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ret i64 %res
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}
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declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone
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define i64 @test_x86_avx512_cvtsd2usi64(<2 x double> %a0) {
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; CHECK: vcvtsd2usiz
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%res = call i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double> %a0) ; <i64> [#uses=1]
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ret i64 %res
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}
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declare i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double>) nounwind readnone
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define <16 x float> @test_x86_vcvtph2ps_512(<16 x i16> %a0) {
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; CHECK: vcvtph2ps
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%res = call <16 x float> @llvm.x86.avx512.vcvtph2ps.512(<16 x i16> %a0)
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.avx512.vcvtph2ps.512(<16 x i16>) nounwind readonly
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define <16 x i16> @test_x86_vcvtps2ph_256(<16 x float> %a0) {
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; CHECK: vcvtps2ph
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%res = call <16 x i16> @llvm.x86.avx512.vcvtps2ph.512(<16 x float> %a0, i32 0)
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ret <16 x i16> %res
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}
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declare <16 x i16> @llvm.x86.avx512.vcvtps2ph.512(<16 x float>, i32) nounwind readonly
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define <16 x float> @test_x86_vbroadcast_ss_512(i8* %a0) {
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; CHECK: vbroadcastss
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%res = call <16 x float> @llvm.x86.avx512.vbroadcast.ss.512(i8* %a0) ; <<16 x float>> [#uses=1]
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.avx512.vbroadcast.ss.512(i8*) nounwind readonly
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define <8 x double> @test_x86_vbroadcast_sd_512(i8* %a0) {
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; CHECK: vbroadcastsd
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%res = call <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8* %a0) ; <<8 x double>> [#uses=1]
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ret <8 x double> %res
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}
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declare <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8*) nounwind readonly
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define <16 x float> @test_x86_vbroadcast_ss_ps_512(<4 x float> %a0) {
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; CHECK: vbroadcastss
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%res = call <16 x float> @llvm.x86.avx512.vbroadcast.ss.ps.512(<4 x float> %a0) ; <<16 x float>> [#uses=1]
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.avx512.vbroadcast.ss.ps.512(<4 x float>) nounwind readonly
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define <8 x double> @test_x86_vbroadcast_sd_pd_512(<2 x double> %a0) {
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; CHECK: vbroadcastsd
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%res = call <8 x double> @llvm.x86.avx512.vbroadcast.sd.pd.512(<2 x double> %a0) ; <<8 x double>> [#uses=1]
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ret <8 x double> %res
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}
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declare <8 x double> @llvm.x86.avx512.vbroadcast.sd.pd.512(<2 x double>) nounwind readonly
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define <16 x i32> @test_x86_pmaxu_d(<16 x i32> %a0, <16 x i32> %a1) {
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; CHECK: vpmaxud
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%res = call <16 x i32> @llvm.x86.avx512.pmaxu.d(<16 x i32> %a0, <16 x i32> %a1) ; <<16 x i32>> [#uses=1]
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ret <16 x i32> %res
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}
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declare <16 x i32> @llvm.x86.avx512.pmaxu.d(<16 x i32>, <16 x i32>) nounwind readonly
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define <8 x i64> @test_x86_pmaxu_q(<8 x i64> %a0, <8 x i64> %a1) {
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; CHECK: vpmaxuq
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%res = call <8 x i64> @llvm.x86.avx512.pmaxu.q(<8 x i64> %a0, <8 x i64> %a1) ; <<8 x i64>> [#uses=1]
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ret <8 x i64> %res
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}
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declare <8 x i64> @llvm.x86.avx512.pmaxu.q(<8 x i64>, <8 x i64>) nounwind readonly
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define <16 x i32> @test_x86_pmaxs_d(<16 x i32> %a0, <16 x i32> %a1) {
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; CHECK: vpmaxsd
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%res = call <16 x i32> @llvm.x86.avx512.pmaxs.d(<16 x i32> %a0, <16 x i32> %a1) ; <<16 x i32>> [#uses=1]
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ret <16 x i32> %res
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}
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declare <16 x i32> @llvm.x86.avx512.pmaxs.d(<16 x i32>, <16 x i32>) nounwind readonly
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define <8 x i64> @test_x86_pmaxs_q(<8 x i64> %a0, <8 x i64> %a1) {
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; CHECK: vpmaxsq
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%res = call <8 x i64> @llvm.x86.avx512.pmaxs.q(<8 x i64> %a0, <8 x i64> %a1) ; <<8 x i64>> [#uses=1]
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ret <8 x i64> %res
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}
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declare <8 x i64> @llvm.x86.avx512.pmaxs.q(<8 x i64>, <8 x i64>) nounwind readonly
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define <16 x i32> @test_x86_pminu_d(<16 x i32> %a0, <16 x i32> %a1) {
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; CHECK: vpminud
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%res = call <16 x i32> @llvm.x86.avx512.pminu.d(<16 x i32> %a0, <16 x i32> %a1) ; <<16 x i32>> [#uses=1]
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ret <16 x i32> %res
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}
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declare <16 x i32> @llvm.x86.avx512.pminu.d(<16 x i32>, <16 x i32>) nounwind readonly
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define <8 x i64> @test_x86_pminu_q(<8 x i64> %a0, <8 x i64> %a1) {
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; CHECK: vpminuq
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%res = call <8 x i64> @llvm.x86.avx512.pminu.q(<8 x i64> %a0, <8 x i64> %a1) ; <<8 x i64>> [#uses=1]
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ret <8 x i64> %res
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}
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declare <8 x i64> @llvm.x86.avx512.pminu.q(<8 x i64>, <8 x i64>) nounwind readonly
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define <16 x i32> @test_x86_pmins_d(<16 x i32> %a0, <16 x i32> %a1) {
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; CHECK: vpminsd
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%res = call <16 x i32> @llvm.x86.avx512.pmins.d(<16 x i32> %a0, <16 x i32> %a1) ; <<16 x i32>> [#uses=1]
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ret <16 x i32> %res
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}
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declare <16 x i32> @llvm.x86.avx512.pmins.d(<16 x i32>, <16 x i32>) nounwind readonly
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define <8 x i64> @test_x86_pmins_q(<8 x i64> %a0, <8 x i64> %a1) {
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; CHECK: vpminsq
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%res = call <8 x i64> @llvm.x86.avx512.pmins.q(<8 x i64> %a0, <8 x i64> %a1) ; <<8 x i64>> [#uses=1]
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ret <8 x i64> %res
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}
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declare <8 x i64> @llvm.x86.avx512.pmins.q(<8 x i64>, <8 x i64>) nounwind readonly
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