Vincent Lejeune cae6801b7d R600: Turn BUILD_VECTOR into Reg_Sequence ... Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176487 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-05 15:04:49 +00:00
..
AArch64	AArch64: be more careful resorting to inefficient addressing for weak vars.	2013-02-28 14:36:31 +00:00
ARM	ARM NEON: Fix v2f32 float intrinsics	2013-03-02 19:38:33 +00:00
CPP
Generic
Hexagon	Hexagon: Add constant extender support framework.	2013-03-01 17:37:13 +00:00
MBlaze
Mips	llvm/test/CodeGen/Mips/mips64-f128.ll: Add explicit -mtriple=mips64el-unknown-unknown to appease win32.	2013-03-05 02:18:59 +00:00
MSP430
NVPTX
PowerPC	Fix PR15332 (patch by Florian Zeitz).	2013-02-26 21:28:57 +00:00
R600	R600: Turn BUILD_VECTOR into Reg_Sequence	2013-03-05 15:04:49 +00:00
SI
SPARC
Thumb	llvm/test/CodeGen/Thumb/iabs.ll: Add explicit -mtriple=thumb-unknown-unknown to appease win32 hosts.	2013-03-05 02:18:52 +00:00
Thumb2	ARM: Creating a vector from a lane of another.	2013-03-02 20:16:24 +00:00
X86	Bypass Slow Divides	2013-03-04 18:13:57 +00:00
XCore