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disassembled output alongside the instructions. E.g., on a vector shuffle operation with a memory operand, disassembled outputs are: * Without the option: vpshufd $-0x79, (%rsp), %xmm0 * With the option: vpshufd $-0x79, (%rsp), %xmm0 ## Latency: 5 The printed latency is extracted from the schedule model available in the disassembler context. Thus, this option has no effect if there is not a scheduling model for the target. This boils down to one may need to specify the CPU string, so that this option could have an effect. Note: Latency < 2 are not printed. This part of <rdar://problem/14687488>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191859 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
Analysis | ||
AsmParser | ||
Bitcode | ||
CodeGen | ||
DebugInfo | ||
ExecutionEngine | ||
IR | ||
IRReader | ||
Linker | ||
LTO | ||
MC | ||
Object | ||
Option | ||
Support | ||
TableGen | ||
Target | ||
Transforms | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
Makefile |