mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-06 05:06:45 +00:00
f8fd883fd3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178083 91177308-0d34-0410-b5e6-96231b3b80d8
40 lines
1.5 KiB
TableGen
40 lines
1.5 KiB
TableGen
//===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file describes the instructions that make up the Intel TSX instruction
|
|
// set.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// TSX instructions
|
|
|
|
def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>,
|
|
[SDNPHasChain, SDNPSideEffect]>;
|
|
|
|
let usesCustomInserter = 1 in
|
|
def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
|
|
"# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>,
|
|
Requires<[HasRTM]>;
|
|
|
|
let isBranch = 1, isTerminator = 1, Defs = [EAX] in
|
|
def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget:$dst),
|
|
"xbegin\t$dst", []>, Requires<[HasRTM]>;
|
|
|
|
def XEND : I<0x01, MRM_D5, (outs), (ins),
|
|
"xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
|
|
|
|
let Defs = [EFLAGS] in
|
|
def XTEST : I<0x01, MRM_D6, (outs), (ins),
|
|
"xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
|
|
|
|
def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
|
|
"xabort\t$imm",
|
|
[(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>;
|