llvm-6502/lib/Target/Sparc
Chris Lattner 7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 05:18:47 +00:00
..
TargetInfo
CMakeLists.txt Use explicit add_subdirectory's for LLVM target sublibraries instead 2011-02-20 02:55:27 +00:00
DelaySlotFiller.cpp Generate correct Sparc32 ABI compliant code for functions that return a struct. 2011-02-21 03:42:44 +00:00
FPMover.cpp
Makefile
README.txt
Sparc.h
Sparc.td
SparcAsmPrinter.cpp
SparcCallingConv.td Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI. 2011-01-22 13:05:16 +00:00
SparcFrameLowering.cpp
SparcFrameLowering.h
SparcInstrFormats.td
SparcInstrInfo.cpp
SparcInstrInfo.h
SparcInstrInfo.td Generate correct Sparc32 ABI compliant code for functions that return a struct. 2011-02-21 03:42:44 +00:00
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp Fix a ton of comment typos found by codespell. Patch by 2011-04-15 05:18:47 +00:00
SparcISelLowering.h Generate correct Sparc32 ABI compliant code for functions that return a struct. 2011-02-21 03:42:44 +00:00
SparcMachineFunctionInfo.h Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI. 2011-01-22 13:05:16 +00:00
SparcMCAsmInfo.cpp
SparcMCAsmInfo.h
SparcRegisterInfo.cpp
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp add support for the sparcv9-*-* target triple to turn on 2010-02-04 06:34:01 +00:00
SparcSubtarget.h
SparcTargetMachine.cpp
SparcTargetMachine.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support