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https://github.com/c64scene-ar/llvm-6502.git
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974a445bd9
subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198685 91177308-0d34-0410-b5e6-96231b3b80d8
317 lines
10 KiB
C++
317 lines
10 KiB
C++
//===-- Mips16ISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips16 ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsDAGToDAGISel specialized for mips16.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-isel"
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#include "Mips16ISelDAGToDAG.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "Mips.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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if (!Subtarget.inMips16Mode())
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return false;
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return MipsDAGToDAGISel::runOnMachineFunction(MF);
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}
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/// Select multiply instructions.
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std::pair<SDNode*, SDNode*>
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Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
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bool HasLo, bool HasHi) {
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SDNode *Lo = 0, *Hi = 0;
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SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
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N->getOperand(1));
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SDValue InFlag = SDValue(Mul, 0);
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if (HasLo) {
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unsigned Opcode = Mips::Mflo16;
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Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
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InFlag = SDValue(Lo, 1);
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}
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if (HasHi) {
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unsigned Opcode = Mips::Mfhi16;
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Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
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}
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return std::make_pair(Lo, Hi);
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}
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void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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if (!MipsFI->globalBaseRegSet())
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return;
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator I = MBB.begin();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
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const TargetRegisterClass *RC =
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(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
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V0 = RegInfo.createVirtualRegister(RC);
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V1 = RegInfo.createVirtualRegister(RC);
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V2 = RegInfo.createVirtualRegister(RC);
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BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0).
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addReg(V1, RegState::Define).
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addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI).
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addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
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BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
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BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
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.addReg(V1).addReg(V2);
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}
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// Insert instructions to initialize the Mips16 SP Alias register in the
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// first MBB of the function.
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//
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void Mips16DAGToDAGISel::initMips16SPAliasReg(MachineFunction &MF) {
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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if (!MipsFI->mips16SPAliasRegSet())
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return;
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator I = MBB.begin();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg();
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BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
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.addReg(Mips::SP);
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}
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void Mips16DAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
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initGlobalBaseReg(MF);
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initMips16SPAliasReg(MF);
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}
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/// getMips16SPAliasReg - Output the instructions required to put the
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/// SP into a Mips16 accessible aliased register.
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SDValue Mips16DAGToDAGISel::getMips16SPAliasReg() {
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unsigned Mips16SPAliasReg =
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MF->getInfo<MipsFunctionInfo>()->getMips16SPAliasReg();
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return CurDAG->getRegister(Mips16SPAliasReg,
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getTargetLowering()->getPointerTy());
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}
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void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
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SDValue AliasFPReg = CurDAG->getRegister(Mips::S0,
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getTargetLowering()->getPointerTy());
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if (Parent) {
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switch (Parent->getOpcode()) {
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case ISD::LOAD: {
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LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent);
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switch (SD->getMemoryVT().getSizeInBits()) {
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case 8:
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case 16:
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AliasReg = TM.getFrameLowering()->hasFP(*MF)?
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AliasFPReg: getMips16SPAliasReg();
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return;
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}
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break;
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}
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case ISD::STORE: {
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StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent);
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switch (SD->getMemoryVT().getSizeInBits()) {
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case 8:
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case 16:
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AliasReg = TM.getFrameLowering()->hasFP(*MF)?
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AliasFPReg: getMips16SPAliasReg();
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return;
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}
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break;
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}
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}
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}
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AliasReg = CurDAG->getRegister(Mips::SP, getTargetLowering()->getPointerTy());
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return;
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}
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bool Mips16DAGToDAGISel::selectAddr16(
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SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
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SDValue &Alias) {
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EVT ValTy = Addr.getValueType();
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Alias = CurDAG->getTargetConstant(0, ValTy);
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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Offset = CurDAG->getTargetConstant(0, ValTy);
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getMips16SPRefReg(Parent, Alias);
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return true;
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}
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// on PIC code Load GA
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if (Addr.getOpcode() == MipsISD::Wrapper) {
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Base = Addr.getOperand(0);
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Offset = Addr.getOperand(1);
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return true;
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}
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if (TM.getRelocationModel() != Reloc::PIC_) {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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}
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// Addresses of the form FI+const or FI|const
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<16>(CN->getSExtValue())) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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getMips16SPRefReg(Parent, Alias);
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}
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else
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
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return true;
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}
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}
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD) {
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// When loading from constant pools, load the lower address part in
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// the instruction itself. Example, instead of:
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// lui $2, %hi($CPI1_0)
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// addiu $2, $2, %lo($CPI1_0)
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// lwc1 $f0, 0($2)
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// Generate:
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// lui $2, %hi($CPI1_0)
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// lwc1 $f0, %lo($CPI1_0)($2)
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if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
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Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
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SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
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if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
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isa<JumpTableSDNode>(Opnd0)) {
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Base = Addr.getOperand(0);
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Offset = Opnd0;
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return true;
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}
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}
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// If an indexed floating point load/store can be emitted, return false.
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const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
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if (LS &&
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(LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
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Subtarget.hasFPIdx())
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return false;
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, ValTy);
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return true;
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}
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/// Select instructions not customized! Used for
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/// expanded, promoted and normal instructions
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std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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SDLoc DL(Node);
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///
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// Instruction Selection not handled by the auto-generated
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// tablegen selection should be handled here.
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///
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EVT NodeTy = Node->getValueType(0);
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unsigned MultOpc;
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switch(Opcode) {
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default: break;
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case ISD::SUBE:
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case ISD::ADDE: {
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SDValue InFlag = Node->getOperand(2), CmpLHS;
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unsigned Opc = InFlag.getOpcode(); (void)Opc;
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assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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(Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
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"(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
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unsigned MOp;
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if (Opcode == ISD::ADDE) {
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CmpLHS = InFlag.getValue(0);
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MOp = Mips::AdduRxRyRz16;
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} else {
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CmpLHS = InFlag.getOperand(0);
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MOp = Mips::SubuRxRyRz16;
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}
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SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
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SDValue LHS = Node->getOperand(0);
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SDValue RHS = Node->getOperand(1);
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EVT VT = LHS.getValueType();
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unsigned Sltu_op = Mips::SltuRxRyRz16;
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SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops);
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unsigned Addu_op = Mips::AdduRxRyRz16;
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SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
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SDValue(Carry,0), RHS);
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SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
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SDValue(AddCarry,0));
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return std::make_pair(true, Result);
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}
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/// Mul with two results
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case ISD::SMUL_LOHI:
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case ISD::UMUL_LOHI: {
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MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
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std::pair<SDNode*, SDNode*> LoHi = selectMULT(Node, MultOpc, DL, NodeTy,
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true, true);
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if (!SDValue(Node, 0).use_empty())
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ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
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if (!SDValue(Node, 1).use_empty())
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ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
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return std::make_pair(true, (SDNode*)NULL);
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}
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case ISD::MULHS:
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case ISD::MULHU: {
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MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
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SDNode *Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second;
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return std::make_pair(true, Result);
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}
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}
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return std::make_pair(false, (SDNode*)NULL);
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}
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FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
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return new Mips16DAGToDAGISel(TM);
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}
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