llvm-6502/test/CodeGen
2013-06-07 00:03:36 +00:00
..
AArch64 Change how we iterate over relocations on ELF. 2013-05-30 03:05:14 +00:00
ARM Cortex-R5 can issue Thumb2 integer division instructions. 2013-06-04 22:52:09 +00:00
CPP
Generic Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen. 2013-05-21 14:37:16 +00:00
Hexagon Hexagon: Pass to replace tranfer/copy instructions into combine instruction 2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips [mips] brcond + setgt/setugt instruction selection patterns. 2013-06-05 19:49:55 +00:00
MSP430 DAGCombiner: Simplify inverted bit tests 2013-05-08 06:44:42 +00:00
NVPTX [NVPTX] Re-enable support for virtual registers in the final output 2013-05-31 12:14:49 +00:00
PowerPC Change how we iterate over relocations on ELF. 2013-05-30 03:05:14 +00:00
R600 R600: Add a pass that merge Vector Register 2013-06-05 21:38:04 +00:00
SI
SPARC [Sparc]: Use cmp instruction instead of subcc to compare integers. 2013-06-07 00:03:36 +00:00
SystemZ [SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses 2013-05-31 13:25:22 +00:00
Thumb
Thumb2 Cortex-R5 can issue Thumb2 integer division instructions. 2013-06-04 22:52:09 +00:00
X86 [PATCH] Fix VGATHER* operand constraints 2013-06-05 18:12:26 +00:00
XCore [XCore] Fix handling of functions where only the LR is spilled. 2013-05-09 16:43:42 +00:00