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https://github.com/c64scene-ar/llvm-6502.git
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da8ac5fd91
Instead, just create one, and make sure everything that needs it can access it. Previously most of the SelectionDAGISel subclasses all had their own TargetLowering object, which was redundant with the TargetLowering object in the TargetMachine subclasses, except on Sparc, where SparcTargetMachine didn't have a TargetLowering object. Change Sparc to work more like the other targets here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8
865 lines
32 KiB
C++
865 lines
32 KiB
C++
//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the ARM target.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMISelLowering.h"
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#include "ARMTargetMachine.h"
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#include "ARMAddressingModes.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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//===--------------------------------------------------------------------===//
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/// ARMDAGToDAGISel - ARM specific code to select ARM machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class ARMDAGToDAGISel : public SelectionDAGISel {
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ARMTargetMachine &TM;
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const ARMSubtarget *Subtarget;
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public:
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explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
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: SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
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Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
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}
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virtual const char *getPassName() const {
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return "ARM Instruction Selection";
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}
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SDNode *Select(SDValue Op);
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virtual void InstructionSelect();
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bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Offset, SDValue &Opc);
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bool SelectAddrMode2Offset(SDValue Op, SDValue N,
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SDValue &Offset, SDValue &Opc);
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bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Offset, SDValue &Opc);
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bool SelectAddrMode3Offset(SDValue Op, SDValue N,
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SDValue &Offset, SDValue &Opc);
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bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Offset);
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bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
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SDValue &Label);
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bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Offset);
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bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
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SDValue &Base, SDValue &OffImm,
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SDValue &Offset);
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bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
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SDValue &OffImm, SDValue &Offset);
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bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
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SDValue &OffImm, SDValue &Offset);
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bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
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SDValue &OffImm, SDValue &Offset);
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bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
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SDValue &OffImm);
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bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
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SDValue &B, SDValue &C);
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// Include the pieces autogenerated from the target description.
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#include "ARMGenDAGISel.inc"
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};
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}
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void ARMDAGToDAGISel::InstructionSelect() {
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DEBUG(BB->dump());
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SelectRoot();
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CurDAG->RemoveDeadNodes();
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}
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bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
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SDValue &Base, SDValue &Offset,
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SDValue &Opc) {
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if (N.getOpcode() == ISD::MUL) {
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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// X * [3,5,9] -> X + X * [2,4,8] etc.
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int RHSC = (int)RHS->getZExtValue();
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if (RHSC & 1) {
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RHSC = RHSC & ~1;
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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if (RHSC < 0) {
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AddSub = ARM_AM::sub;
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RHSC = - RHSC;
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}
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if (isPowerOf2_32(RHSC)) {
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unsigned ShAmt = Log2_32(RHSC);
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Base = Offset = N.getOperand(0);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
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ARM_AM::lsl),
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MVT::i32);
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return true;
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}
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}
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}
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}
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if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
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Base = N;
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if (N.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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} else if (N.getOpcode() == ARMISD::Wrapper) {
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Base = N.getOperand(0);
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}
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
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ARM_AM::no_shift),
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MVT::i32);
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return true;
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}
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// Match simple R +/- imm12 operands.
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if (N.getOpcode() == ISD::ADD)
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC >= 0 && RHSC < 0x1000) ||
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(RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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Offset = CurDAG->getRegister(0, MVT::i32);
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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if (RHSC < 0) {
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AddSub = ARM_AM::sub;
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RHSC = - RHSC;
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}
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
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ARM_AM::no_shift),
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MVT::i32);
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return true;
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}
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}
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// Otherwise this is R +/- [possibly shifted] R
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ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
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ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
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unsigned ShAmt = 0;
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Base = N.getOperand(0);
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Offset = N.getOperand(1);
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if (ShOpcVal != ARM_AM::no_shift) {
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// Check to see if the RHS of the shift is a constant, if not, we can't fold
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// it.
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if (ConstantSDNode *Sh =
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dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
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ShAmt = Sh->getZExtValue();
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Offset = N.getOperand(1).getOperand(0);
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} else {
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ShOpcVal = ARM_AM::no_shift;
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}
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}
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// Try matching (R shl C) + (R).
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if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
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ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
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if (ShOpcVal != ARM_AM::no_shift) {
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// Check to see if the RHS of the shift is a constant, if not, we can't
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// fold it.
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if (ConstantSDNode *Sh =
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dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
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ShAmt = Sh->getZExtValue();
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Offset = N.getOperand(0).getOperand(0);
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Base = N.getOperand(1);
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} else {
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ShOpcVal = ARM_AM::no_shift;
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}
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}
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}
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
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MVT::i32);
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return true;
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}
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bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
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SDValue &Offset, SDValue &Opc) {
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unsigned Opcode = Op.getOpcode();
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ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
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? cast<LoadSDNode>(Op)->getAddressingMode()
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: cast<StoreSDNode>(Op)->getAddressingMode();
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ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
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? ARM_AM::add : ARM_AM::sub;
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
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int Val = (int)C->getZExtValue();
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if (Val >= 0 && Val < 0x1000) { // 12 bits.
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
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ARM_AM::no_shift),
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MVT::i32);
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return true;
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}
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}
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Offset = N;
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ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
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unsigned ShAmt = 0;
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if (ShOpcVal != ARM_AM::no_shift) {
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// Check to see if the RHS of the shift is a constant, if not, we can't fold
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// it.
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if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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ShAmt = Sh->getZExtValue();
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Offset = N.getOperand(0);
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} else {
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ShOpcVal = ARM_AM::no_shift;
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}
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}
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
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MVT::i32);
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return true;
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}
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bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
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SDValue &Base, SDValue &Offset,
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SDValue &Opc) {
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if (N.getOpcode() == ISD::SUB) {
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// X - C is canonicalize to X + -C, no need to handle it here.
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Base = N.getOperand(0);
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Offset = N.getOperand(1);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
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return true;
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}
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if (N.getOpcode() != ISD::ADD) {
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Base = N;
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if (N.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
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return true;
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}
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// If the RHS is +/- imm8, fold into addr mode.
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC >= 0 && RHSC < 256) ||
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(RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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Offset = CurDAG->getRegister(0, MVT::i32);
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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if (RHSC < 0) {
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AddSub = ARM_AM::sub;
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RHSC = - RHSC;
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}
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
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return true;
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}
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}
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Base = N.getOperand(0);
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Offset = N.getOperand(1);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
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return true;
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}
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bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
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SDValue &Offset, SDValue &Opc) {
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unsigned Opcode = Op.getOpcode();
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ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
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? cast<LoadSDNode>(Op)->getAddressingMode()
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: cast<StoreSDNode>(Op)->getAddressingMode();
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ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
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? ARM_AM::add : ARM_AM::sub;
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
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int Val = (int)C->getZExtValue();
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if (Val >= 0 && Val < 256) {
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Offset = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
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return true;
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}
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}
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Offset = N;
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
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return true;
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}
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bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
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SDValue &Base, SDValue &Offset) {
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if (N.getOpcode() != ISD::ADD) {
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Base = N;
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if (N.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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} else if (N.getOpcode() == ARMISD::Wrapper) {
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Base = N.getOperand(0);
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}
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Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
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MVT::i32);
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return true;
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}
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// If the RHS is +/- imm8, fold into addr mode.
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
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RHSC >>= 2;
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if ((RHSC >= 0 && RHSC < 256) ||
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(RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
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}
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ARM_AM::AddrOpc AddSub = ARM_AM::add;
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if (RHSC < 0) {
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AddSub = ARM_AM::sub;
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RHSC = - RHSC;
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}
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Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
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MVT::i32);
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return true;
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}
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}
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}
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Base = N;
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Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
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MVT::i32);
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return true;
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}
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bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
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SDValue &Offset, SDValue &Label) {
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if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
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Offset = N.getOperand(0);
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SDValue N1 = N.getOperand(1);
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Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
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MVT::i32);
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return true;
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}
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return false;
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}
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bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
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SDValue &Base, SDValue &Offset){
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if (N.getOpcode() != ISD::ADD) {
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Base = N;
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// We must materialize a zero in a reg! Returning an constant here won't
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// work since its node is -1 so it won't get added to the selection queue.
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// Explicitly issue a tMOVri8 node!
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Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
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CurDAG->getTargetConstant(0, MVT::i32)), 0);
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return true;
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}
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Base = N.getOperand(0);
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Offset = N.getOperand(1);
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return true;
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}
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bool
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ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
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unsigned Scale, SDValue &Base,
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SDValue &OffImm, SDValue &Offset) {
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if (Scale == 4) {
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SDValue TmpBase, TmpOffImm;
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if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
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return false; // We want to select tLDRspi / tSTRspi instead.
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if (N.getOpcode() == ARMISD::Wrapper &&
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N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
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return false; // We want to select tLDRpci instead.
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}
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if (N.getOpcode() != ISD::ADD) {
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Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
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Offset = CurDAG->getRegister(0, MVT::i32);
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OffImm = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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// Thumb does not have [sp, r] address mode.
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RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
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RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
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if ((LHSR && LHSR->getReg() == ARM::SP) ||
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(RHSR && RHSR->getReg() == ARM::SP)) {
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Base = N;
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Offset = CurDAG->getRegister(0, MVT::i32);
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OffImm = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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// If the RHS is + imm5 * scale, fold into addr mode.
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if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
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RHSC /= Scale;
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if (RHSC >= 0 && RHSC < 32) {
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Base = N.getOperand(0);
|
|
Offset = CurDAG->getRegister(0, MVT::i32);
|
|
OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
Base = N.getOperand(0);
|
|
Offset = N.getOperand(1);
|
|
OffImm = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
|
|
SDValue &Base, SDValue &OffImm,
|
|
SDValue &Offset) {
|
|
return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
|
|
}
|
|
|
|
bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
|
|
SDValue &Base, SDValue &OffImm,
|
|
SDValue &Offset) {
|
|
return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
|
|
}
|
|
|
|
bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
|
|
SDValue &Base, SDValue &OffImm,
|
|
SDValue &Offset) {
|
|
return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
|
|
}
|
|
|
|
bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
|
|
SDValue &Base, SDValue &OffImm) {
|
|
if (N.getOpcode() == ISD::FrameIndex) {
|
|
int FI = cast<FrameIndexSDNode>(N)->getIndex();
|
|
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
|
|
OffImm = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
if (N.getOpcode() != ISD::ADD)
|
|
return false;
|
|
|
|
RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
|
|
if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
|
|
(LHSR && LHSR->getReg() == ARM::SP)) {
|
|
// If the RHS is + imm8 * scale, fold into addr mode.
|
|
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
|
|
int RHSC = (int)RHS->getZExtValue();
|
|
if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
|
|
RHSC >>= 2;
|
|
if (RHSC >= 0 && RHSC < 256) {
|
|
Base = N.getOperand(0);
|
|
if (Base.getOpcode() == ISD::FrameIndex) {
|
|
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
|
|
Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
|
|
}
|
|
OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
|
|
SDValue N,
|
|
SDValue &BaseReg,
|
|
SDValue &ShReg,
|
|
SDValue &Opc) {
|
|
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
|
|
|
|
// Don't match base register only case. That is matched to a separate
|
|
// lower complexity pattern with explicit register operand.
|
|
if (ShOpcVal == ARM_AM::no_shift) return false;
|
|
|
|
BaseReg = N.getOperand(0);
|
|
unsigned ShImmVal = 0;
|
|
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
|
|
ShReg = CurDAG->getRegister(0, MVT::i32);
|
|
ShImmVal = RHS->getZExtValue() & 31;
|
|
} else {
|
|
ShReg = N.getOperand(1);
|
|
}
|
|
Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
|
|
MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
/// getAL - Returns a ARMCC::AL immediate node.
|
|
static inline SDValue getAL(SelectionDAG *CurDAG) {
|
|
return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
|
|
}
|
|
|
|
|
|
SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
|
|
SDNode *N = Op.getNode();
|
|
|
|
if (N->isMachineOpcode())
|
|
return NULL; // Already selected.
|
|
|
|
switch (N->getOpcode()) {
|
|
default: break;
|
|
case ISD::Constant: {
|
|
unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
|
|
bool UseCP = true;
|
|
if (Subtarget->isThumb())
|
|
UseCP = (Val > 255 && // MOV
|
|
~Val > 255 && // MOV + MVN
|
|
!ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
|
|
else
|
|
UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
|
|
ARM_AM::getSOImmVal(~Val) == -1 && // MVN
|
|
!ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
|
|
if (UseCP) {
|
|
SDValue CPIdx =
|
|
CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
|
|
TLI.getPointerTy());
|
|
|
|
SDNode *ResNode;
|
|
if (Subtarget->isThumb())
|
|
ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other,
|
|
CPIdx, CurDAG->getEntryNode());
|
|
else {
|
|
SDValue Ops[] = {
|
|
CPIdx,
|
|
CurDAG->getRegister(0, MVT::i32),
|
|
CurDAG->getTargetConstant(0, MVT::i32),
|
|
getAL(CurDAG),
|
|
CurDAG->getRegister(0, MVT::i32),
|
|
CurDAG->getEntryNode()
|
|
};
|
|
ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6);
|
|
}
|
|
ReplaceUses(Op, SDValue(ResNode, 0));
|
|
return NULL;
|
|
}
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
}
|
|
case ISD::FrameIndex: {
|
|
// Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
|
|
int FI = cast<FrameIndexSDNode>(N)->getIndex();
|
|
SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
|
|
if (Subtarget->isThumb())
|
|
return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
|
|
CurDAG->getTargetConstant(0, MVT::i32));
|
|
else {
|
|
SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
|
|
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
|
|
CurDAG->getRegister(0, MVT::i32) };
|
|
return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
|
|
}
|
|
}
|
|
case ISD::ADD: {
|
|
// Select add sp, c to tADDhirr.
|
|
SDValue N0 = Op.getOperand(0);
|
|
SDValue N1 = Op.getOperand(1);
|
|
RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
|
|
RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
|
|
if (LHSR && LHSR->getReg() == ARM::SP) {
|
|
std::swap(N0, N1);
|
|
std::swap(LHSR, RHSR);
|
|
}
|
|
if (RHSR && RHSR->getReg() == ARM::SP) {
|
|
AddToISelQueue(N0);
|
|
AddToISelQueue(N1);
|
|
return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), N0, N1);
|
|
}
|
|
break;
|
|
}
|
|
case ISD::MUL:
|
|
if (Subtarget->isThumb())
|
|
break;
|
|
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
|
|
unsigned RHSV = C->getZExtValue();
|
|
if (!RHSV) break;
|
|
if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
|
|
SDValue V = Op.getOperand(0);
|
|
AddToISelQueue(V);
|
|
unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
|
|
SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
|
|
CurDAG->getTargetConstant(ShImm, MVT::i32),
|
|
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
|
|
CurDAG->getRegister(0, MVT::i32) };
|
|
return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
|
|
}
|
|
if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
|
|
SDValue V = Op.getOperand(0);
|
|
AddToISelQueue(V);
|
|
unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
|
|
SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
|
|
CurDAG->getTargetConstant(ShImm, MVT::i32),
|
|
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
|
|
CurDAG->getRegister(0, MVT::i32) };
|
|
return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
|
|
}
|
|
}
|
|
break;
|
|
case ARMISD::FMRRD:
|
|
AddToISelQueue(Op.getOperand(0));
|
|
return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32,
|
|
Op.getOperand(0), getAL(CurDAG),
|
|
CurDAG->getRegister(0, MVT::i32));
|
|
case ISD::UMUL_LOHI: {
|
|
AddToISelQueue(Op.getOperand(0));
|
|
AddToISelQueue(Op.getOperand(1));
|
|
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
|
|
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
|
|
CurDAG->getRegister(0, MVT::i32) };
|
|
return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5);
|
|
}
|
|
case ISD::SMUL_LOHI: {
|
|
AddToISelQueue(Op.getOperand(0));
|
|
AddToISelQueue(Op.getOperand(1));
|
|
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
|
|
getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
|
|
CurDAG->getRegister(0, MVT::i32) };
|
|
return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5);
|
|
}
|
|
case ISD::LOAD: {
|
|
LoadSDNode *LD = cast<LoadSDNode>(Op);
|
|
ISD::MemIndexedMode AM = LD->getAddressingMode();
|
|
MVT LoadedVT = LD->getMemoryVT();
|
|
if (AM != ISD::UNINDEXED) {
|
|
SDValue Offset, AMOpc;
|
|
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
|
|
unsigned Opcode = 0;
|
|
bool Match = false;
|
|
if (LoadedVT == MVT::i32 &&
|
|
SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
|
|
Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
|
|
Match = true;
|
|
} else if (LoadedVT == MVT::i16 &&
|
|
SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
|
|
Match = true;
|
|
Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
|
|
? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
|
|
: (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
|
|
} else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
|
|
if (LD->getExtensionType() == ISD::SEXTLOAD) {
|
|
if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
|
|
Match = true;
|
|
Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
|
|
}
|
|
} else {
|
|
if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
|
|
Match = true;
|
|
Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (Match) {
|
|
SDValue Chain = LD->getChain();
|
|
SDValue Base = LD->getBasePtr();
|
|
AddToISelQueue(Chain);
|
|
AddToISelQueue(Base);
|
|
AddToISelQueue(Offset);
|
|
SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
|
|
CurDAG->getRegister(0, MVT::i32), Chain };
|
|
return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
|
|
MVT::Other, Ops, 6);
|
|
}
|
|
}
|
|
// Other cases are autogenerated.
|
|
break;
|
|
}
|
|
case ARMISD::BRCOND: {
|
|
// Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
|
|
// Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
|
|
// Pattern complexity = 6 cost = 1 size = 0
|
|
|
|
// Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
|
|
// Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
|
|
// Pattern complexity = 6 cost = 1 size = 0
|
|
|
|
unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
|
|
SDValue Chain = Op.getOperand(0);
|
|
SDValue N1 = Op.getOperand(1);
|
|
SDValue N2 = Op.getOperand(2);
|
|
SDValue N3 = Op.getOperand(3);
|
|
SDValue InFlag = Op.getOperand(4);
|
|
assert(N1.getOpcode() == ISD::BasicBlock);
|
|
assert(N2.getOpcode() == ISD::Constant);
|
|
assert(N3.getOpcode() == ISD::Register);
|
|
|
|
AddToISelQueue(Chain);
|
|
AddToISelQueue(N1);
|
|
AddToISelQueue(InFlag);
|
|
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
|
|
cast<ConstantSDNode>(N2)->getZExtValue()),
|
|
MVT::i32);
|
|
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
|
|
SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
|
|
Chain = SDValue(ResNode, 0);
|
|
if (Op.getNode()->getNumValues() == 2) {
|
|
InFlag = SDValue(ResNode, 1);
|
|
ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
|
|
}
|
|
ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
|
|
return NULL;
|
|
}
|
|
case ARMISD::CMOV: {
|
|
bool isThumb = Subtarget->isThumb();
|
|
MVT VT = Op.getValueType();
|
|
SDValue N0 = Op.getOperand(0);
|
|
SDValue N1 = Op.getOperand(1);
|
|
SDValue N2 = Op.getOperand(2);
|
|
SDValue N3 = Op.getOperand(3);
|
|
SDValue InFlag = Op.getOperand(4);
|
|
assert(N2.getOpcode() == ISD::Constant);
|
|
assert(N3.getOpcode() == ISD::Register);
|
|
|
|
// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
|
|
// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
|
|
// Pattern complexity = 18 cost = 1 size = 0
|
|
SDValue CPTmp0;
|
|
SDValue CPTmp1;
|
|
SDValue CPTmp2;
|
|
if (!isThumb && VT == MVT::i32 &&
|
|
SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
|
|
AddToISelQueue(N0);
|
|
AddToISelQueue(CPTmp0);
|
|
AddToISelQueue(CPTmp1);
|
|
AddToISelQueue(CPTmp2);
|
|
AddToISelQueue(InFlag);
|
|
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
|
|
cast<ConstantSDNode>(N2)->getZExtValue()),
|
|
MVT::i32);
|
|
SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
|
|
return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
|
|
}
|
|
|
|
// Pattern: (ARMcmov:i32 GPR:i32:$false,
|
|
// (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true,
|
|
// (imm:i32):$cc)
|
|
// Emits: (MOVCCi:i32 GPR:i32:$false,
|
|
// (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc)
|
|
// Pattern complexity = 10 cost = 1 size = 0
|
|
if (VT == MVT::i32 &&
|
|
N3.getOpcode() == ISD::Constant &&
|
|
Predicate_so_imm(N3.getNode())) {
|
|
AddToISelQueue(N0);
|
|
AddToISelQueue(InFlag);
|
|
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
|
|
cast<ConstantSDNode>(N1)->getZExtValue()),
|
|
MVT::i32);
|
|
Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
|
|
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
|
|
cast<ConstantSDNode>(N2)->getZExtValue()),
|
|
MVT::i32);
|
|
SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
|
|
return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
|
|
}
|
|
|
|
// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
|
|
// Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
|
|
// Pattern complexity = 6 cost = 1 size = 0
|
|
//
|
|
// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
|
|
// Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
|
|
// Pattern complexity = 6 cost = 11 size = 0
|
|
//
|
|
// Also FCPYScc and FCPYDcc.
|
|
AddToISelQueue(N0);
|
|
AddToISelQueue(N1);
|
|
AddToISelQueue(InFlag);
|
|
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
|
|
cast<ConstantSDNode>(N2)->getZExtValue()),
|
|
MVT::i32);
|
|
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
|
|
unsigned Opc = 0;
|
|
switch (VT.getSimpleVT()) {
|
|
default: assert(false && "Illegal conditional move type!");
|
|
break;
|
|
case MVT::i32:
|
|
Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr;
|
|
break;
|
|
case MVT::f32:
|
|
Opc = ARM::FCPYScc;
|
|
break;
|
|
case MVT::f64:
|
|
Opc = ARM::FCPYDcc;
|
|
break;
|
|
}
|
|
return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
|
|
}
|
|
case ARMISD::CNEG: {
|
|
MVT VT = Op.getValueType();
|
|
SDValue N0 = Op.getOperand(0);
|
|
SDValue N1 = Op.getOperand(1);
|
|
SDValue N2 = Op.getOperand(2);
|
|
SDValue N3 = Op.getOperand(3);
|
|
SDValue InFlag = Op.getOperand(4);
|
|
assert(N2.getOpcode() == ISD::Constant);
|
|
assert(N3.getOpcode() == ISD::Register);
|
|
|
|
AddToISelQueue(N0);
|
|
AddToISelQueue(N1);
|
|
AddToISelQueue(InFlag);
|
|
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
|
|
cast<ConstantSDNode>(N2)->getZExtValue()),
|
|
MVT::i32);
|
|
SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
|
|
unsigned Opc = 0;
|
|
switch (VT.getSimpleVT()) {
|
|
default: assert(false && "Illegal conditional move type!");
|
|
break;
|
|
case MVT::f32:
|
|
Opc = ARM::FNEGScc;
|
|
break;
|
|
case MVT::f64:
|
|
Opc = ARM::FNEGDcc;
|
|
break;
|
|
}
|
|
return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
|
|
}
|
|
}
|
|
return SelectCode(Op);
|
|
}
|
|
|
|
/// createARMISelDag - This pass converts a legalized DAG into a
|
|
/// ARM-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createARMISelDag(ARMTargetMachine &TM) {
|
|
return new ARMDAGToDAGISel(TM);
|
|
}
|