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https://github.com/c64scene-ar/llvm-6502.git
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86245071b5
Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
337 lines
8.2 KiB
C++
337 lines
8.2 KiB
C++
//===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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// \file
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//===----------------------------------------------------------------------===//
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#include "AMDGPUInstPrinter.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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using namespace llvm;
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void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
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StringRef Annot) {
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OS.flush();
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printInstruction(MI, OS);
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printAnnotation(OS, Annot);
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}
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void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
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switch (reg) {
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case AMDGPU::VCC:
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O << "vcc";
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return;
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case AMDGPU::SCC:
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O << "scc";
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return;
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case AMDGPU::EXEC:
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O << "exec";
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return;
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case AMDGPU::M0:
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O << "m0";
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return;
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default:
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break;
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}
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// It's seems there's no way to use SIRegisterInfo here, and dealing with the
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// giant enum of all the different shifted sets of registers is pretty
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// unmanagable, so parse the name and reformat it to be prettier.
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StringRef Name(getRegisterName(reg));
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std::pair<StringRef, StringRef> Split = Name.split('_');
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StringRef SubRegName = Split.first;
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StringRef Rest = Split.second;
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if (SubRegName.size() <= 4) { // Must at least be as long as "SGPR"/"VGPR".
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O << Name;
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return;
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}
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unsigned RegIndex;
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StringRef RegIndexStr = SubRegName.drop_front(4);
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if (RegIndexStr.getAsInteger(10, RegIndex)) {
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O << Name;
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return;
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}
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if (SubRegName.front() == 'V')
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O << 'v';
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else if (SubRegName.front() == 'S')
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O << 's';
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else {
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O << Name;
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return;
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}
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if (Rest.empty()) // Only 1 32-bit register
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O << RegIndex;
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else {
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unsigned NumReg = Rest.count('_') + 2;
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O << '[' << RegIndex << ':' << (RegIndex + NumReg - 1) << ']';
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}
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}
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void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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switch (Op.getReg()) {
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// This is the default predicate state, so we don't need to print it.
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case AMDGPU::PRED_SEL_OFF:
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break;
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default:
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printRegOperand(Op.getReg(), O);
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break;
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}
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} else if (Op.isImm()) {
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O << Op.getImm();
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} else if (Op.isFPImm()) {
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O << Op.getFPImm();
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} else if (Op.isExpr()) {
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const MCExpr *Exp = Op.getExpr();
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Exp->print(O);
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} else {
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assert(!"unknown operand type in printOperand");
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}
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}
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void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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unsigned Imm = MI->getOperand(OpNum).getImm();
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if (Imm == 2) {
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O << "P0";
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} else if (Imm == 1) {
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O << "P20";
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} else if (Imm == 0) {
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O << "P10";
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} else {
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assert(!"Invalid interpolation parameter slot");
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}
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}
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void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printOperand(MI, OpNo, O);
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O << ", ";
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printOperand(MI, OpNo + 1, O);
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}
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void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, StringRef Asm,
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StringRef Default) {
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const MCOperand &Op = MI->getOperand(OpNo);
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assert(Op.isImm());
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if (Op.getImm() == 1) {
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O << Asm;
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} else {
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O << Default;
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}
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}
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void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "|");
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}
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void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "_SAT");
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}
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void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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union Literal {
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float f;
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int32_t i;
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} L;
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L.i = MI->getOperand(OpNo).getImm();
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O << L.i << "(" << L.f << ")";
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}
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void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O.indent(25 - O.GetNumBytesInBuffer()), "*", " ");
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}
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void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "-");
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}
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void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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switch (MI->getOperand(OpNo).getImm()) {
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default: break;
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case 1:
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O << " * 2.0";
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break;
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case 2:
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O << " * 4.0";
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break;
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case 3:
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O << " / 2.0";
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break;
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}
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}
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void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "+");
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}
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void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "ExecMask,");
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}
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void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "Pred,");
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}
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void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.getImm() == 0) {
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O << " (MASKED)";
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}
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}
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void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const char * chans = "XYZW";
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int sel = MI->getOperand(OpNo).getImm();
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int chan = sel & 3;
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sel >>= 2;
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if (sel >= 512) {
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sel -= 512;
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int cb = sel >> 12;
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sel &= 4095;
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O << cb << "[" << sel << "]";
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} else if (sel >= 448) {
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sel -= 448;
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O << sel;
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} else if (sel >= 0){
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O << sel;
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}
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if (sel >= 0)
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O << "." << chans[chan];
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}
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void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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int BankSwizzle = MI->getOperand(OpNo).getImm();
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switch (BankSwizzle) {
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case 1:
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O << "BS:VEC_021/SCL_122";
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break;
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case 2:
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O << "BS:VEC_120/SCL_212";
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break;
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case 3:
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O << "BS:VEC_102/SCL_221";
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break;
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case 4:
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O << "BS:VEC_201";
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break;
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case 5:
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O << "BS:VEC_210";
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break;
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default:
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break;
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}
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return;
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}
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void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned Sel = MI->getOperand(OpNo).getImm();
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switch (Sel) {
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case 0:
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O << "X";
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break;
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case 1:
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O << "Y";
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break;
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case 2:
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O << "Z";
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break;
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case 3:
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O << "W";
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break;
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case 4:
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O << "0";
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break;
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case 5:
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O << "1";
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break;
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case 7:
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O << "_";
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break;
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default:
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break;
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}
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}
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void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned CT = MI->getOperand(OpNo).getImm();
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switch (CT) {
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case 0:
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O << "U";
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break;
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case 1:
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O << "N";
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break;
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default:
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break;
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}
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}
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void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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int KCacheMode = MI->getOperand(OpNo).getImm();
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if (KCacheMode > 0) {
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int KCacheBank = MI->getOperand(OpNo - 2).getImm();
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O << "CB" << KCacheBank <<":";
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int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
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int LineSize = (KCacheMode == 1)?16:32;
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O << KCacheAddr * 16 << "-" << KCacheAddr * 16 + LineSize;
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}
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}
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void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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// Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
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// SIInsertWaits.cpp bits usage does not match ISA docs description but it
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// works so it might be a misprint in docs.
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unsigned SImm16 = MI->getOperand(OpNo).getImm();
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unsigned Vmcnt = SImm16 & 0xF;
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unsigned Expcnt = (SImm16 >> 4) & 0xF;
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unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
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if (Vmcnt != 0xF)
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O << "vmcnt(" << Vmcnt << ") ";
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if (Expcnt != 0x7)
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O << "expcnt(" << Expcnt << ") ";
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if (Lgkmcnt != 0x7)
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O << "lgkmcnt(" << Lgkmcnt << ")";
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}
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#include "AMDGPUGenAsmWriter.inc"
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