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https://github.com/c64scene-ar/llvm-6502.git
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7d8867d453
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145422 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
1.9 KiB
C++
59 lines
1.9 KiB
C++
//===-- ARMHazardRecognizer.h - ARM Hazard Recognizers ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines hazard recognizers for scheduling ARM functions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMHAZARDRECOGNIZER_H
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#define ARMHAZARDRECOGNIZER_H
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#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
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namespace llvm {
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class ARMBaseInstrInfo;
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class ARMBaseRegisterInfo;
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class ARMSubtarget;
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class MachineInstr;
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/// ARMHazardRecognizer handles special constraints that are not expressed in
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/// the scheduling itinerary. This is only used during postRA scheduling. The
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/// ARM preRA scheduler uses an unspecialized instance of the
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/// ScoreboardHazardRecognizer.
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class ARMHazardRecognizer : public ScoreboardHazardRecognizer {
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const ARMBaseInstrInfo &TII;
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const ARMBaseRegisterInfo &TRI;
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const ARMSubtarget &STI;
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MachineInstr *LastMI;
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unsigned FpMLxStalls;
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unsigned ITBlockSize; // No. of MIs in current IT block yet to be scheduled.
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MachineInstr *ITBlockMIs[4];
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public:
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ARMHazardRecognizer(const InstrItineraryData *ItinData,
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const ARMBaseInstrInfo &tii,
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const ARMBaseRegisterInfo &tri,
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const ARMSubtarget &sti,
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const ScheduleDAG *DAG) :
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ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
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TRI(tri), STI(sti), LastMI(0), ITBlockSize(0) {}
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virtual HazardType getHazardType(SUnit *SU, int Stalls);
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virtual void Reset();
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virtual void EmitInstruction(SUnit *SU);
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virtual void AdvanceCycle();
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virtual void RecedeCycle();
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};
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} // end namespace llvm
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#endif // ARMHAZARDRECOGNIZER_H
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