Jakob Stoklund Olesen 63e6a488cb If the first definition of a virtual register is a partial redef, add an ...

<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320 91177308-0d34-0410-b5e6-96231b3b80d8

2010-05-21 16:32:16 +00:00

..

Analysis.h

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AsmPrinter.h

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BinaryObject.h

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CalcSpillWeights.h

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CallingConvLower.h

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FastISel.h

Add initial kill flag support to FastISel.

2010-05-11 23:54:07 +00:00

GCMetadata.h

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GCMetadataPrinter.h

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GCs.h

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GCStrategy.h

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IntrinsicLowering.h

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ISDOpcodes.h

Elaborate on a comment.

2010-04-29 16:57:54 +00:00

JITCodeEmitter.h

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LatencyPriorityQueue.h

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LinkAllAsmWriterComponents.h

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LinkAllCodegenComponents.h

Add a hybrid bottom up scheduler that reduce register usage while avoiding

2010-05-20 06:13:19 +00:00

LiveInterval.h

Removed scaleNumbering method declaration from LiveInterval (not defined, not used).

2010-05-21 03:04:04 +00:00

LiveIntervalAnalysis.h

Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g.

2010-05-05 18:27:40 +00:00

LiveStackAnalysis.h

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LiveVariables.h

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MachineBasicBlock.h

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MachineCodeEmitter.h

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MachineCodeInfo.h

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MachineConstantPool.h

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MachineDominators.h

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MachineFrameInfo.h

Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what

2010-05-14 21:14:32 +00:00

MachineFunction.h

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MachineFunctionAnalysis.h

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MachineFunctionPass.h

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MachineInstr.h

If the first definition of a virtual register is a partial redef, add an

2010-05-21 16:32:16 +00:00

MachineInstrBuilder.h

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MachineJumpTableInfo.h

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MachineLocation.h

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MachineLoopInfo.h

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MachineMemOperand.h

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MachineModuleInfo.h

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MachineModuleInfoImpls.h

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MachineOperand.h

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MachinePassRegistry.h

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MachineRegisterInfo.h

Add reg_nodbg_iterator

2010-05-15 02:52:58 +00:00

MachineRelocation.h

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MachineSSAUpdater.h

Combine the implementations of the core part of the SSAUpdater and

2010-05-04 23:18:19 +00:00

MachORelocation.h

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ObjectCodeEmitter.h

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Passes.h

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ProcessImplicitDefs.h

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PseudoSourceValue.h

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RegAllocRegistry.h

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RegisterCoalescer.h

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RegisterScavenging.h

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RuntimeLibcalls.h

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ScheduleDAG.h

Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.

2010-05-20 23:26:43 +00:00

ScheduleHazardRecognizer.h

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SchedulerRegistry.h

Add a hybrid bottom up scheduler that reduce register usage while avoiding

2010-05-20 06:13:19 +00:00

SelectionDAG.h

Implement a bunch more TargetSelectionDAGInfo infrastructure.

2010-05-11 17:31:57 +00:00

SelectionDAGISel.h

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SelectionDAGNodes.h

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SlotIndexes.h

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TargetLoweringObjectFileImpl.h

More data/parsing support for tls directives. Add a few more testcases

2010-05-17 22:53:55 +00:00

ValueTypes.h

Fix enum to address array bounds regression.

2010-05-18 21:22:12 +00:00

ValueTypes.td

Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.

2010-05-13 23:55:47 +00:00