mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 22:04:55 +00:00
700ed80d3d
to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
43 lines
1.2 KiB
C++
43 lines
1.2 KiB
C++
//===-- MipsSERegisterInfo.h - Mips32/64 Register Information ---*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the Mips32/64 implementation of the TargetRegisterInfo
|
|
// class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef MIPSSEREGISTERINFO_H
|
|
#define MIPSSEREGISTERINFO_H
|
|
|
|
#include "MipsRegisterInfo.h"
|
|
|
|
namespace llvm {
|
|
class MipsSEInstrInfo;
|
|
|
|
class MipsSERegisterInfo : public MipsRegisterInfo {
|
|
const MipsSEInstrInfo &TII;
|
|
|
|
public:
|
|
MipsSERegisterInfo(const MipsSubtarget &Subtarget,
|
|
const MipsSEInstrInfo &TII);
|
|
|
|
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
|
|
|
bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
|
|
|
|
private:
|
|
virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
|
|
int FrameIndex, uint64_t StackSize,
|
|
int64_t SPOffset) const;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|