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0e407e7bbf
Summary: The loop which emits AssemblerPredicate conditions also links them together by emitting a '&&'. If the 1st predicate is not an AssemblerPredicate, while the 2nd one is, nothing gets emitted for the 1st one, but we still emit the '&&' because of the 2nd predicate. This generated code looks like "( && Cond2)" and is invalid. Reviewers: dsanders Reviewed By: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D8294 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234312 91177308-0d34-0410-b5e6-96231b3b80d8
32 lines
885 B
TableGen
32 lines
885 B
TableGen
// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
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// Check that we don't generate invalid code of the form "( && Cond2)" when
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// emitting AssemblerPredicate conditions. In the example below, the invalid
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// code would be: "return ( && (Bits & arch::AssemblerCondition2));".
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def arch : Target {
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let InstructionSet = archInstrInfo;
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}
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def Pred1 : Predicate<"Condition1">;
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def Pred2 : Predicate<"Condition2">,
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AssemblerPredicate<"AssemblerCondition2">;
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def foo : Instruction {
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let Size = 2;
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let OutOperandList = (outs);
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let InOperandList = (ins);
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field bits<16> Inst;
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let Inst = 0xAAAA;
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let AsmString = "foo";
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field bits<16> SoftFail = 0;
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// This is the important bit:
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let Predicates = [Pred1, Pred2];
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}
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// CHECK: return ((Bits & arch::AssemblerCondition2));
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