mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-28 04:33:05 +00:00
045573ce21
Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.
This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110744 91177308-0d34-0410-b5e6-96231b3b80d8
406 lines
18 KiB
TableGen
406 lines
18 KiB
TableGen
//======- X86InstrFragmentsSIMD.td - x86 ISA -------------*- tablegen -*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides pattern fragments useful for SIMD instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MMX Pattern Fragments
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//===----------------------------------------------------------------------===//
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def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
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def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
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def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
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def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
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def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
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//===----------------------------------------------------------------------===//
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// MMX Masks
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//===----------------------------------------------------------------------===//
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// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
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// PSHUFW imm.
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def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShuffleSHUFImmediate(N));
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}]>;
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// Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
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def mmx_unpckh : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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// Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
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def mmx_unpckl : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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// Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
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def mmx_unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
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}]>;
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// Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
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def mmx_unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def mmx_pshufw : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
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}], MMX_SHUFFLE_get_shuf_imm>;
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//===----------------------------------------------------------------------===//
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// SSE specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
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SDTCisFP<0>, SDTCisInt<2> ]>;
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def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
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SDTCisFP<1>, SDTCisVT<3, i8>]>;
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def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
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def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
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def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
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def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
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def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
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def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
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def X86pshufb : SDNode<"X86ISD::PSHUFB",
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SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86pextrb : SDNode<"X86ISD::PEXTRB",
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
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def X86pextrw : SDNode<"X86ISD::PEXTRW",
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
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def X86pinsrb : SDNode<"X86ISD::PINSRB",
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SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
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def X86pinsrw : SDNode<"X86ISD::PINSRW",
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SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
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def X86insrtps : SDNode<"X86ISD::INSERTPS",
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SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
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SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
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def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
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SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
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def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
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[SDNPHasChain, SDNPMayLoad]>;
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def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
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def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
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def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
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def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
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def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
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def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
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def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
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def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
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def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
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SDTCisVec<1>,
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SDTCisSameAs<2, 1>]>;
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def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
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def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
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//===----------------------------------------------------------------------===//
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// SSE Complex Patterns
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//===----------------------------------------------------------------------===//
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// These are 'extloads' from a scalar to the low element of a vector, zeroing
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// the top elements. These are used for the SSE 'ss' and 'sd' instruction
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// forms.
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def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
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[SDNPHasChain, SDNPMayLoad]>;
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def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
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[SDNPHasChain, SDNPMayLoad]>;
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def ssmem : Operand<v4f32> {
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let PrintMethod = "printf32mem";
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let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
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let ParserMatchClass = X86MemAsmOperand;
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}
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def sdmem : Operand<v2f64> {
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let PrintMethod = "printf64mem";
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let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
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let ParserMatchClass = X86MemAsmOperand;
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}
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//===----------------------------------------------------------------------===//
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// SSE pattern fragments
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//===----------------------------------------------------------------------===//
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def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
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def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
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def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
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def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
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// FIXME: move this to a more appropriate place after all AVX is done.
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def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
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def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
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def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>;
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def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
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// Like 'store', but always requires vector alignment.
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def alignedstore : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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return cast<StoreSDNode>(N)->getAlignment() >= 16;
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}]>;
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// Like 'load', but always requires vector alignment.
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def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return cast<LoadSDNode>(N)->getAlignment() >= 16;
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}]>;
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def alignedloadfsf32 : PatFrag<(ops node:$ptr),
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(f32 (alignedload node:$ptr))>;
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def alignedloadfsf64 : PatFrag<(ops node:$ptr),
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(f64 (alignedload node:$ptr))>;
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def alignedloadv4f32 : PatFrag<(ops node:$ptr),
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(v4f32 (alignedload node:$ptr))>;
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def alignedloadv2f64 : PatFrag<(ops node:$ptr),
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(v2f64 (alignedload node:$ptr))>;
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def alignedloadv4i32 : PatFrag<(ops node:$ptr),
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(v4i32 (alignedload node:$ptr))>;
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def alignedloadv2i64 : PatFrag<(ops node:$ptr),
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(v2i64 (alignedload node:$ptr))>;
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// FIXME: move this to a more appropriate place after all AVX is done.
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def alignedloadv8f32 : PatFrag<(ops node:$ptr),
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(v8f32 (alignedload node:$ptr))>;
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def alignedloadv4f64 : PatFrag<(ops node:$ptr),
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(v4f64 (alignedload node:$ptr))>;
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def alignedloadv8i32 : PatFrag<(ops node:$ptr),
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(v8i32 (alignedload node:$ptr))>;
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def alignedloadv4i64 : PatFrag<(ops node:$ptr),
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(v4i64 (alignedload node:$ptr))>;
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// Like 'load', but uses special alignment checks suitable for use in
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// memory operands in most SSE instructions, which are required to
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// be naturally aligned on some targets but not on others. If the subtarget
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// allows unaligned accesses, match any load, though this may require
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// setting a feature bit in the processor (on startup, for example).
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// Opteron 10h and later implement such a feature.
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def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return Subtarget->hasVectorUAMem()
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|| cast<LoadSDNode>(N)->getAlignment() >= 16;
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}]>;
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def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
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def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
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def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
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def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
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def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
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def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
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def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
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// FIXME: move this to a more appropriate place after all AVX is done.
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def memopv32i8 : PatFrag<(ops node:$ptr), (v32i8 (memop node:$ptr))>;
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def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
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def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
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def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
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def memopv8i32 : PatFrag<(ops node:$ptr), (v8i32 (memop node:$ptr))>;
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// SSSE3 uses MMX registers for some instructions. They aren't aligned on a
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// 16-byte boundary.
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// FIXME: 8 byte alignment for mmx reads is not required
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def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return cast<LoadSDNode>(N)->getAlignment() >= 8;
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}]>;
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def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
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def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
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def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
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def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
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// MOVNT Support
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// Like 'store', but requires the non-temporal bit to be set
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def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
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return ST->isNonTemporal();
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return false;
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}]>;
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def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
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return ST->isNonTemporal() && !ST->isTruncatingStore() &&
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ST->getAddressingMode() == ISD::UNINDEXED &&
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ST->getAlignment() >= 16;
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return false;
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}]>;
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def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
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return ST->isNonTemporal() &&
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ST->getAlignment() < 16;
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return false;
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}]>;
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def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
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def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
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def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
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def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
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def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
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def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
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// FIXME: move this to a more appropriate place after all AVX is done.
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def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
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def vzmovl_v2i64 : PatFrag<(ops node:$src),
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(bitconvert (v2i64 (X86vzmovl
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(v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
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def vzmovl_v4i32 : PatFrag<(ops node:$src),
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(bitconvert (v4i32 (X86vzmovl
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(v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
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def vzload_v2i64 : PatFrag<(ops node:$src),
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(bitconvert (v2i64 (X86vzload node:$src)))>;
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def fp32imm0 : PatLeaf<(f32 fpimm), [{
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return N->isExactlyValue(+0.0);
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}]>;
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// BYTE_imm - Transform bit immediates into byte immediates.
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def BYTE_imm : SDNodeXForm<imm, [{
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// Transformation function: imm >> 3
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return getI32Imm(N->getZExtValue() >> 3);
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}]>;
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// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
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// SHUFP* etc. imm.
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def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShuffleSHUFImmediate(N));
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}]>;
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// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
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// PSHUFHW imm.
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def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
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}]>;
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// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
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// PSHUFLW imm.
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def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
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}]>;
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// SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
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// a PALIGNR imm.
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def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShufflePALIGNRImmediate(N));
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}]>;
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def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
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return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
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}]>;
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def movddup : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movlp : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movl : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
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}]>;
|
|
|
|
def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(vector_shuffle node:$lhs, node:$rhs), [{
|
|
return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
|
|
}]>;
|
|
|
|
def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(vector_shuffle node:$lhs, node:$rhs), [{
|
|
return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
|
|
}]>;
|
|
|
|
def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(vector_shuffle node:$lhs, node:$rhs), [{
|
|
return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
|
|
}]>;
|
|
|
|
def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(vector_shuffle node:$lhs, node:$rhs), [{
|
|
return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
|
|
}]>;
|
|
|
|
def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(vector_shuffle node:$lhs, node:$rhs), [{
|
|
return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
|
|
}]>;
|
|
|
|
def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(vector_shuffle node:$lhs, node:$rhs), [{
|
|
return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
|
|
}]>;
|
|
|
|
def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(vector_shuffle node:$lhs, node:$rhs), [{
|
|
return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
|
|
}], SHUFFLE_get_shuf_imm>;
|
|
|
|
def shufp : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(vector_shuffle node:$lhs, node:$rhs), [{
|
|
return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
|
|
}], SHUFFLE_get_shuf_imm>;
|
|
|
|
def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(vector_shuffle node:$lhs, node:$rhs), [{
|
|
return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
|
|
}], SHUFFLE_get_pshufhw_imm>;
|
|
|
|
def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(vector_shuffle node:$lhs, node:$rhs), [{
|
|
return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
|
|
}], SHUFFLE_get_pshuflw_imm>;
|
|
|
|
def palign : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(vector_shuffle node:$lhs, node:$rhs), [{
|
|
return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
|
|
}], SHUFFLE_get_palign_imm>;
|