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https://github.com/c64scene-ar/llvm-6502.git
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642eccbb21
All string occurences for "sparc", "Sparc" and "SPARC" were already replaced, with the exception of ELF constans in the object file descriptor as it will get removed later on (we won't be building ELF object files for the 6502).
455 lines
16 KiB
C++
455 lines
16 KiB
C++
//===-- Mos6502InstrInfo.cpp - Mos6502 Instruction Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mos6502 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mos6502InstrInfo.h"
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#include "Mos6502.h"
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#include "Mos6502MachineFunctionInfo.h"
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#include "Mos6502Subtarget.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "Mos6502GenInstrInfo.inc"
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// Pin the vtable to this file.
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void Mos6502InstrInfo::anchor() {}
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Mos6502InstrInfo::Mos6502InstrInfo(Mos6502Subtarget &ST)
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: Mos6502GenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
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Subtarget(ST) {}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned Mos6502InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == SP::LDri ||
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MI->getOpcode() == SP::LDXri ||
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MI->getOpcode() == SP::LDFri ||
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MI->getOpcode() == SP::LDDFri ||
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MI->getOpcode() == SP::LDQFri) {
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if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned Mos6502InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == SP::STri ||
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MI->getOpcode() == SP::STXri ||
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MI->getOpcode() == SP::STFri ||
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MI->getOpcode() == SP::STDFri ||
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MI->getOpcode() == SP::STQFri) {
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if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
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MI->getOperand(1).getImm() == 0) {
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FrameIndex = MI->getOperand(0).getIndex();
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return MI->getOperand(2).getReg();
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}
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}
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return 0;
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}
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static bool IsIntegerCC(unsigned CC)
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{
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return (CC <= SPCC::ICC_VC);
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}
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static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
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{
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switch(CC) {
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case SPCC::ICC_A: return SPCC::ICC_N;
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case SPCC::ICC_N: return SPCC::ICC_A;
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case SPCC::ICC_NE: return SPCC::ICC_E;
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case SPCC::ICC_E: return SPCC::ICC_NE;
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case SPCC::ICC_G: return SPCC::ICC_LE;
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case SPCC::ICC_LE: return SPCC::ICC_G;
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case SPCC::ICC_GE: return SPCC::ICC_L;
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case SPCC::ICC_L: return SPCC::ICC_GE;
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case SPCC::ICC_GU: return SPCC::ICC_LEU;
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case SPCC::ICC_LEU: return SPCC::ICC_GU;
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case SPCC::ICC_CC: return SPCC::ICC_CS;
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case SPCC::ICC_CS: return SPCC::ICC_CC;
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case SPCC::ICC_POS: return SPCC::ICC_NEG;
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case SPCC::ICC_NEG: return SPCC::ICC_POS;
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case SPCC::ICC_VC: return SPCC::ICC_VS;
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case SPCC::ICC_VS: return SPCC::ICC_VC;
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case SPCC::FCC_A: return SPCC::FCC_N;
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case SPCC::FCC_N: return SPCC::FCC_A;
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case SPCC::FCC_U: return SPCC::FCC_O;
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case SPCC::FCC_O: return SPCC::FCC_U;
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case SPCC::FCC_G: return SPCC::FCC_ULE;
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case SPCC::FCC_LE: return SPCC::FCC_UG;
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case SPCC::FCC_UG: return SPCC::FCC_LE;
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case SPCC::FCC_ULE: return SPCC::FCC_G;
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case SPCC::FCC_L: return SPCC::FCC_UGE;
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case SPCC::FCC_GE: return SPCC::FCC_UL;
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case SPCC::FCC_UL: return SPCC::FCC_GE;
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case SPCC::FCC_UGE: return SPCC::FCC_L;
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case SPCC::FCC_LG: return SPCC::FCC_UE;
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case SPCC::FCC_UE: return SPCC::FCC_LG;
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case SPCC::FCC_NE: return SPCC::FCC_E;
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case SPCC::FCC_E: return SPCC::FCC_NE;
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}
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llvm_unreachable("Invalid cond code");
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}
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bool Mos6502InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const
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{
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MachineBasicBlock::iterator I = MBB.end();
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MachineBasicBlock::iterator UnCondBrIter = MBB.end();
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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// When we see a non-terminator, we are done.
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if (!isUnpredicatedTerminator(I))
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break;
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// Terminator is not a branch.
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if (!I->isBranch())
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return true;
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// Handle Unconditional branches.
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if (I->getOpcode() == SP::BA) {
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UnCondBrIter = I;
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if (!AllowModify) {
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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while (std::next(I) != MBB.end())
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std::next(I)->eraseFromParent();
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Cond.clear();
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FBB = nullptr;
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if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
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TBB = nullptr;
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I->eraseFromParent();
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I = MBB.end();
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UnCondBrIter = MBB.end();
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continue;
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}
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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unsigned Opcode = I->getOpcode();
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if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
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return true; // Unknown Opcode.
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SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
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if (Cond.empty()) {
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MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
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if (AllowModify && UnCondBrIter != MBB.end() &&
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MBB.isLayoutSuccessor(TargetBB)) {
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// Transform the code
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//
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// brCC L1
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// ba L2
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// L1:
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// ..
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// L2:
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//
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// into
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//
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// brnCC L2
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// L1:
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// ...
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// L2:
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//
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BranchCode = GetOppositeBranchCondition(BranchCode);
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MachineBasicBlock::iterator OldInst = I;
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BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
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.addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
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BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
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.addMBB(TargetBB);
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OldInst->eraseFromParent();
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UnCondBrIter->eraseFromParent();
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UnCondBrIter = MBB.end();
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I = MBB.end();
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continue;
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}
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FBB = TBB;
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TBB = I->getOperand(0).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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continue;
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}
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// FIXME: Handle subsequent conditional branches.
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// For now, we can't handle multiple conditional branches.
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return true;
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}
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return false;
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}
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unsigned
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Mos6502InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const {
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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"Mos6502 branch conditions should have one component!");
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if (Cond.empty()) {
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
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return 1;
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}
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// Conditional branch
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unsigned CC = Cond[0].getImm();
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if (IsIntegerCC(CC))
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BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
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else
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BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
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if (!FBB)
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return 1;
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BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
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return 2;
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}
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unsigned Mos6502InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
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{
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MachineBasicBlock::iterator I = MBB.end();
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unsigned Count = 0;
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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if (I->getOpcode() != SP::BA
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&& I->getOpcode() != SP::BCOND
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&& I->getOpcode() != SP::FBCOND)
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break; // Not a branch
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I->eraseFromParent();
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I = MBB.end();
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++Count;
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}
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return Count;
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}
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void Mos6502InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned numSubRegs = 0;
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unsigned movOpc = 0;
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const unsigned *subRegIdx = nullptr;
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const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
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const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
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const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
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SP::sub_odd64_then_sub_even,
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SP::sub_odd64_then_sub_odd };
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if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
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BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
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BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
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if (Subtarget.isV9()) {
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BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else {
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// Use two FMOVS instructions.
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subRegIdx = DFP_FP_SubRegsIdx;
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numSubRegs = 2;
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movOpc = SP::FMOVS;
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}
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} else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
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if (Subtarget.isV9()) {
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if (Subtarget.hasHardQuad()) {
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BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else {
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// Use two FMOVD instructions.
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subRegIdx = QFP_DFP_SubRegsIdx;
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numSubRegs = 2;
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movOpc = SP::FMOVD;
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}
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} else {
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// Use four FMOVS instructions.
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subRegIdx = QFP_FP_SubRegsIdx;
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numSubRegs = 4;
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movOpc = SP::FMOVS;
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}
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} else if (SP::ASRRegsRegClass.contains(DestReg) &&
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SP::IntRegsRegClass.contains(SrcReg)) {
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BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
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.addReg(SP::G0)
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else if (SP::IntRegsRegClass.contains(DestReg) &&
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SP::ASRRegsRegClass.contains(SrcReg)) {
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BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else
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llvm_unreachable("Impossible reg-to-reg copy");
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if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
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return;
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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MachineInstr *MovMI = nullptr;
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for (unsigned i = 0; i != numSubRegs; ++i) {
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unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
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unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
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assert(Dst && Src && "Bad sub-register");
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MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src);
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}
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// Add implicit super-register defs and kills to the last MovMI.
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MovMI->addRegisterDefined(DestReg, TRI);
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if (KillSrc)
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MovMI->addRegisterKilled(SrcReg, TRI);
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}
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void Mos6502InstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction *MF = MBB.getParent();
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const MachineFrameInfo &MFI = *MF->getFrameInfo();
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MachineMemOperand *MMO =
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MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOStore,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
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if (RC == &SP::I64RegsRegClass)
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BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else if (RC == &SP::IntRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else if (RC == &SP::FPRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
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BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
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// Use STQFri irrespective of its legality. If STQ is not legal, it will be
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// lowered into two STDs in eliminateFrameIndex.
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BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
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else
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llvm_unreachable("Can't store this register to stack slot");
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}
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void Mos6502InstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction *MF = MBB.getParent();
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const MachineFrameInfo &MFI = *MF->getFrameInfo();
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MachineMemOperand *MMO =
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MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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if (RC == &SP::I64RegsRegClass)
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BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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else if (RC == &SP::IntRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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else if (RC == &SP::FPRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
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BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
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// Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
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// lowered into two LDDs in eliminateFrameIndex.
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BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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else
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llvm_unreachable("Can't load this register from stack slot");
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}
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unsigned Mos6502InstrInfo::getGlobalBaseReg(MachineFunction *MF) const
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{
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Mos6502MachineFunctionInfo *Mos6502FI = MF->getInfo<Mos6502MachineFunctionInfo>();
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unsigned GlobalBaseReg = Mos6502FI->getGlobalBaseReg();
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if (GlobalBaseReg != 0)
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return GlobalBaseReg;
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = MF->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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const TargetRegisterClass *PtrRC =
|
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Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
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|
GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
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|
|
|
DebugLoc dl;
|
|
|
|
BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
|
|
Mos6502FI->setGlobalBaseReg(GlobalBaseReg);
|
|
return GlobalBaseReg;
|
|
}
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