mirror of
https://github.com/c64scene-ar/llvm-6502.git
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dec5091220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227474 91177308-0d34-0410-b5e6-96231b3b80d8
134 lines
6.2 KiB
TableGen
134 lines
6.2 KiB
TableGen
//===- HexagonIntrinsicsV5.td - V4 Instruction intrinsics --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def : T_FF_pat<F2_sfadd, int_hexagon_F2_sfadd>;
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def : T_FF_pat<F2_sfsub, int_hexagon_F2_sfsub>;
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def : T_FF_pat<F2_sfmpy, int_hexagon_F2_sfmpy>;
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def : T_FF_pat<F2_sfmax, int_hexagon_F2_sfmax>;
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def : T_FF_pat<F2_sfmin, int_hexagon_F2_sfmin>;
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def : T_FF_pat<F2_sffixupn, int_hexagon_F2_sffixupn>;
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def : T_FF_pat<F2_sffixupd, int_hexagon_F2_sffixupd>;
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def : T_F_pat <F2_sffixupr, int_hexagon_F2_sffixupr>;
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def: qi_CRInst_qiqi_pat<C4_fastcorner9, int_hexagon_C4_fastcorner9>;
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def: qi_CRInst_qiqi_pat<C4_fastcorner9_not, int_hexagon_C4_fastcorner9_not>;
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def : T_P_pat <S5_popcountp, int_hexagon_S5_popcountp>;
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def : T_PI_pat <S5_asrhub_sat, int_hexagon_S5_asrhub_sat>;
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def : T_PI_pat <S2_asr_i_p_rnd, int_hexagon_S2_asr_i_p_rnd>;
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def : T_PI_pat <S2_asr_i_p_rnd_goodsyntax,
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int_hexagon_S2_asr_i_p_rnd_goodsyntax>;
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def : T_PI_pat <S5_asrhub_rnd_sat_goodsyntax,
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int_hexagon_S5_asrhub_rnd_sat_goodsyntax>;
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def : T_FFF_pat <F2_sffma, int_hexagon_F2_sffma>;
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def : T_FFF_pat <F2_sffms, int_hexagon_F2_sffms>;
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def : T_FFF_pat <F2_sffma_lib, int_hexagon_F2_sffma_lib>;
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def : T_FFF_pat <F2_sffms_lib, int_hexagon_F2_sffms_lib>;
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def : T_FFFQ_pat <F2_sffma_sc, int_hexagon_F2_sffma_sc>;
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// Compare floating-point value
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def : T_FF_pat <F2_sfcmpge, int_hexagon_F2_sfcmpge>;
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def : T_FF_pat <F2_sfcmpuo, int_hexagon_F2_sfcmpuo>;
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def : T_FF_pat <F2_sfcmpeq, int_hexagon_F2_sfcmpeq>;
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def : T_FF_pat <F2_sfcmpgt, int_hexagon_F2_sfcmpgt>;
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def : T_DD_pat <F2_dfcmpeq, int_hexagon_F2_dfcmpeq>;
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def : T_DD_pat <F2_dfcmpgt, int_hexagon_F2_dfcmpgt>;
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def : T_DD_pat <F2_dfcmpge, int_hexagon_F2_dfcmpge>;
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def : T_DD_pat <F2_dfcmpuo, int_hexagon_F2_dfcmpuo>;
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// Create floating-point value
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def : T_I_pat <F2_sfimm_p, int_hexagon_F2_sfimm_p>;
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def : T_I_pat <F2_sfimm_n, int_hexagon_F2_sfimm_n>;
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def : T_I_pat <F2_dfimm_p, int_hexagon_F2_dfimm_p>;
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def : T_I_pat <F2_dfimm_n, int_hexagon_F2_dfimm_n>;
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def : T_DI_pat <F2_dfclass, int_hexagon_F2_dfclass>;
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def : T_FI_pat <F2_sfclass, int_hexagon_F2_sfclass>;
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def : T_F_pat <F2_conv_sf2df, int_hexagon_F2_conv_sf2df>;
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def : T_D_pat <F2_conv_df2sf, int_hexagon_F2_conv_df2sf>;
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def : T_R_pat <F2_conv_uw2sf, int_hexagon_F2_conv_uw2sf>;
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def : T_R_pat <F2_conv_uw2df, int_hexagon_F2_conv_uw2df>;
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def : T_R_pat <F2_conv_w2sf, int_hexagon_F2_conv_w2sf>;
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def : T_R_pat <F2_conv_w2df, int_hexagon_F2_conv_w2df>;
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def : T_P_pat <F2_conv_ud2sf, int_hexagon_F2_conv_ud2sf>;
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def : T_P_pat <F2_conv_ud2df, int_hexagon_F2_conv_ud2df>;
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def : T_P_pat <F2_conv_d2sf, int_hexagon_F2_conv_d2sf>;
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def : T_P_pat <F2_conv_d2df, int_hexagon_F2_conv_d2df>;
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def : T_F_pat <F2_conv_sf2uw, int_hexagon_F2_conv_sf2uw>;
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def : T_F_pat <F2_conv_sf2w, int_hexagon_F2_conv_sf2w>;
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def : T_F_pat <F2_conv_sf2ud, int_hexagon_F2_conv_sf2ud>;
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def : T_F_pat <F2_conv_sf2d, int_hexagon_F2_conv_sf2d>;
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def : T_D_pat <F2_conv_df2uw, int_hexagon_F2_conv_df2uw>;
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def : T_D_pat <F2_conv_df2w, int_hexagon_F2_conv_df2w>;
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def : T_D_pat <F2_conv_df2ud, int_hexagon_F2_conv_df2ud>;
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def : T_D_pat <F2_conv_df2d, int_hexagon_F2_conv_df2d>;
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def : T_F_pat <F2_conv_sf2uw_chop, int_hexagon_F2_conv_sf2uw_chop>;
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def : T_F_pat <F2_conv_sf2w_chop, int_hexagon_F2_conv_sf2w_chop>;
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def : T_F_pat <F2_conv_sf2ud_chop, int_hexagon_F2_conv_sf2ud_chop>;
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def : T_F_pat <F2_conv_sf2d_chop, int_hexagon_F2_conv_sf2d_chop>;
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def : T_D_pat <F2_conv_df2uw_chop, int_hexagon_F2_conv_df2uw_chop>;
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def : T_D_pat <F2_conv_df2w_chop, int_hexagon_F2_conv_df2w_chop>;
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def : T_D_pat <F2_conv_df2ud_chop, int_hexagon_F2_conv_df2ud_chop>;
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def : T_D_pat <F2_conv_df2d_chop, int_hexagon_F2_conv_df2d_chop>;
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class qi_ALU64_dfdf<string opc, Intrinsic IntID>
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: ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
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class qi_ALU64_dfu5<string opc, Intrinsic IntID>
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: ALU64_ri<(outs PredRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
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[(set PredRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
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class qi_SInst_sfsf<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class qi_SInst_sfu5<string opc, Intrinsic IntID>
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: MInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class di_MInst_diu4_rnd<string opc, Intrinsic IntID>
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: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u4Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
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def HEXAGON_M5_vrmpybuu:
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di_MInst_didi <"vrmpybu", int_hexagon_M5_vrmpybuu>;
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def HEXAGON_M5_vrmacbuu:
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di_MInst_dididi_acc <"vrmpybu", int_hexagon_M5_vrmacbuu>;
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def HEXAGON_M5_vrmpybsu:
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di_MInst_didi <"vrmpybsu", int_hexagon_M5_vrmpybsu>;
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def HEXAGON_M5_vrmacbsu:
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di_MInst_dididi_acc <"vrmpybsu", int_hexagon_M5_vrmacbsu>;
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def HEXAGON_M5_vmpybuu:
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di_MInst_sisi <"vmpybu", int_hexagon_M5_vmpybuu>;
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def HEXAGON_M5_vmpybsu:
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di_MInst_sisi <"vmpybsu", int_hexagon_M5_vmpybsu>;
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def HEXAGON_M5_vmacbuu:
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di_MInst_disisi_acc <"vmpybu", int_hexagon_M5_vmacbuu>;
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def HEXAGON_M5_vmacbsu:
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di_MInst_disisi_acc <"vmpybsu", int_hexagon_M5_vmacbsu>;
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def HEXAGON_M5_vdmpybsu:
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di_MInst_didi_sat <"vdmpybsu", int_hexagon_M5_vdmpybsu>;
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def HEXAGON_M5_vdmacbsu:
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di_MInst_dididi_acc_sat <"vdmpybsu", int_hexagon_M5_vdmacbsu>;
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def HEXAGON_A5_vaddhubs:
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si_SInst_didi_sat <"vaddhub", int_hexagon_A5_vaddhubs>;
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def HEXAGON_S5_vasrhrnd_goodsyntax:
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di_MInst_diu4_rnd <"vasrh", int_hexagon_S5_vasrhrnd_goodsyntax>;
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