llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-13 12:57:47 +00:00

History

Evan Cheng d64b5c82b9 Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether the stored register is killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8		2007-12-05 03:14:33 +00:00
..
Alpha.h
Alpha.td
AlphaAsmPrinter.cpp	Eliminate the remaining uses of getTypeSize. This	2007-11-05 00:04:43 +00:00
AlphaBranchSelector.cpp
AlphaCodeEmitter.cpp
AlphaInstrFormats.td
AlphaInstrInfo.cpp
AlphaInstrInfo.h
AlphaInstrInfo.td	something wrong with this opt	2007-11-27 18:31:30 +00:00
AlphaISelDAGToDAG.cpp
AlphaISelLowering.cpp	Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack	2007-11-13 00:44:25 +00:00
AlphaISelLowering.h
AlphaJITInfo.cpp
AlphaJITInfo.h
AlphaLLRP.cpp
AlphaRegisterInfo.cpp	Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether	2007-12-05 03:14:33 +00:00
AlphaRegisterInfo.h	Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether	2007-12-05 03:14:33 +00:00
AlphaRegisterInfo.td	Use TableGen to emit information for dwarf register numbers.	2007-11-11 19:50:10 +00:00
AlphaRelocations.h
AlphaSchedule.td
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetAsmInfo.cpp
AlphaTargetAsmInfo.h	More explicit keywords.	2007-09-25 20:27:06 +00:00
AlphaTargetMachine.cpp
AlphaTargetMachine.h
Makefile
README.txt

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html