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d64b5c82b9
the stored register is killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
547 lines
17 KiB
C++
547 lines
17 KiB
C++
//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Bruno Cardoso Lopes and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-reg-info"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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#include "MipsMachineFunction.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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//#include "MipsSubtarget.h"
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using namespace llvm;
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// TODO: add subtarget support
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MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
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: MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
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TII(tii) {}
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// Mips::RA, return the number that it corresponds to (e.g. 31).
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unsigned MipsRegisterInfo::
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getRegisterNumbering(unsigned RegEnum)
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{
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switch (RegEnum) {
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case Mips::ZERO : return 0;
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case Mips::AT : return 1;
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case Mips::V0 : return 2;
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case Mips::V1 : return 3;
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case Mips::A0 : return 4;
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case Mips::A1 : return 5;
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case Mips::A2 : return 6;
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case Mips::A3 : return 7;
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case Mips::T0 : return 8;
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case Mips::T1 : return 9;
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case Mips::T2 : return 10;
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case Mips::T3 : return 11;
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case Mips::T4 : return 12;
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case Mips::T5 : return 13;
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case Mips::T6 : return 14;
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case Mips::T7 : return 15;
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case Mips::T8 : return 16;
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case Mips::T9 : return 17;
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case Mips::S0 : return 18;
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case Mips::S1 : return 19;
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case Mips::S2 : return 20;
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case Mips::S3 : return 21;
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case Mips::S4 : return 22;
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case Mips::S5 : return 23;
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case Mips::S6 : return 24;
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case Mips::S7 : return 25;
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case Mips::K0 : return 26;
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case Mips::K1 : return 27;
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case Mips::GP : return 28;
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case Mips::SP : return 29;
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case Mips::FP : return 30;
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case Mips::RA : return 31;
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default: assert(0 && "Unknown register number!");
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}
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}
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void MipsRegisterInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const
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{
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, TII.get(Mips::SW)).addReg(SrcReg, false, false, isKill)
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.addImm(0).addFrameIndex(FI);
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else
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assert(0 && "Can't store this register to stack slot");
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}
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void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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if (RC != Mips::CPURegsRegisterClass)
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assert(0 && "Can't store this register");
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MachineInstrBuilder MIB = BuildMI(TII.get(Mips::SW))
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.addReg(SrcReg, false, false, isKill);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImmedValue());
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else
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MIB.addFrameIndex(MO.getFrameIndex());
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}
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NewMIs.push_back(MIB);
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return;
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}
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void MipsRegisterInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const
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{
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, TII.get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
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else
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assert(0 && "Can't load this register from stack slot");
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}
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void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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if (RC != Mips::CPURegsRegisterClass)
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assert(0 && "Can't load this register");
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MachineInstrBuilder MIB = BuildMI(TII.get(Mips::LW), DestReg);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImmedValue());
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else
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MIB.addFrameIndex(MO.getFrameIndex());
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}
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NewMIs.push_back(MIB);
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return;
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}
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void MipsRegisterInfo::
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copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const
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{
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if (DestRC != SrcRC) {
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cerr << "Not yet supported!";
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abort();
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}
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if (DestRC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
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.addReg(SrcReg);
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else
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assert (0 && "Can't copy this register");
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}
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void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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const MachineInstr *Orig) const
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{
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MachineInstr *MI = Orig->clone();
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MI->getOperand(0).setReg(DestReg);
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MBB.insert(I, MI);
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}
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MachineInstr *MipsRegisterInfo::
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foldMemoryOperand(MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops, int FI) const
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{
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if (Ops.size() != 1) return NULL;
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MachineInstr *NewMI = NULL;
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switch (MI->getOpcode())
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{
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case Mips::ADDu:
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if ((MI->getOperand(0).isRegister()) &&
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(MI->getOperand(1).isRegister()) &&
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(MI->getOperand(1).getReg() == Mips::ZERO) &&
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(MI->getOperand(2).isRegister()))
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{
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if (Ops[0] == 0) // COPY -> STORE
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NewMI = BuildMI(TII.get(Mips::SW)).addFrameIndex(FI)
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.addImm(0).addReg(MI->getOperand(2).getReg());
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else // COPY -> LOAD
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NewMI = BuildMI(TII.get(Mips::LW), MI->getOperand(0)
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.getReg()).addImm(0).addFrameIndex(FI);
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}
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break;
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}
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if (NewMI)
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NewMI->copyKillDeadInfo(MI);
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return NewMI;
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}
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//===----------------------------------------------------------------------===//
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//
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// Callee Saved Registers methods
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//
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//===----------------------------------------------------------------------===//
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/// Mips Callee Saved Registers
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const unsigned* MipsRegisterInfo::
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getCalleeSavedRegs(const MachineFunction *MF) const
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{
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// Mips calle-save register range is $16-$26(s0-s7)
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static const unsigned CalleeSavedRegs[] = {
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Mips::S0, Mips::S1, Mips::S2, Mips::S3,
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Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
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};
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return CalleeSavedRegs;
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}
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/// Mips Callee Saved Register Classes
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const TargetRegisterClass* const*
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MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
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{
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static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
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};
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return CalleeSavedRegClasses;
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}
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BitVector MipsRegisterInfo::
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getReservedRegs(const MachineFunction &MF) const
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{
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BitVector Reserved(getNumRegs());
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Reserved.set(Mips::ZERO);
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Reserved.set(Mips::AT);
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Reserved.set(Mips::K0);
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Reserved.set(Mips::K1);
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Reserved.set(Mips::GP);
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Reserved.set(Mips::SP);
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Reserved.set(Mips::FP);
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Reserved.set(Mips::RA);
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return Reserved;
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}
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//===----------------------------------------------------------------------===//
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//
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// Stack Frame Processing methods
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// +----------------------------+
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//
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// The stack is allocated decrementing the stack pointer on
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// the first instruction of a function prologue. Once decremented,
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// all stack referencesare are done thought a positive offset
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// from the stack/frame pointer, so the stack is considering
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// to grow up! Otherwise terrible hacks would have to be made
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// to get this stack ABI compliant :)
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//
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// The stack frame required by the ABI:
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// Offset
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//
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// 0 ----------
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// 4 Args to pass
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// . saved $GP (used in PIC - not supported yet)
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// . Local Area
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// . saved "Callee Saved" Registers
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// . saved FP
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// . saved RA
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// StackSize -----------
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//
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// Offset - offset from sp after stack allocation on function prologue
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//
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// The sp is the stack pointer subtracted/added from the stack size
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// at the Prologue/Epilogue
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//
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// References to the previous stack (to obtain arguments) are done
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// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
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//
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// Examples:
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// - reference to the actual stack frame
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// for any local area var there is smt like : FI >= 0, StackOffset: 4
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// sw REGX, 4(SP)
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//
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// - reference to previous stack frame
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// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
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// The emitted instruction will be something like:
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// lw REGX, 16+StackSize(SP)
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//
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// Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
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// stack references (ObjectOffset) created to reference the function
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// arguments, are negative numbers. This way, on eliminateFrameIndex it's
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// possible to detect those references and the offsets are adjusted to
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// their real location.
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//
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//
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//
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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bool MipsRegisterInfo::
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hasFP(const MachineFunction &MF) const {
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return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
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}
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// This function eliminate ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void MipsRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
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MBB.erase(I);
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}
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
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// direct reference.
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void MipsRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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RegScavenger *RS) const
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{
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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unsigned i = 0;
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() &&
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"Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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int stackSize = MF.getFrameInfo()->getStackSize();
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int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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#ifndef NDEBUG
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DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
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DOUT << "<--------->\n";
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MI.print(DOUT);
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DOUT << "FrameIndex : " << FrameIndex << "\n";
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DOUT << "spOffset : " << spOffset << "\n";
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DOUT << "stackSize : " << stackSize << "\n";
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#endif
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// as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
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// and adjust SPOffsets considering the final stack size.
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int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
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Offset += MI.getOperand(i-1).getImm();
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#ifndef NDEBUG
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DOUT << "Offset : " << Offset << "\n";
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DOUT << "<--------->\n";
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#endif
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MI.getOperand(i-1).ChangeToImmediate(Offset);
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MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
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}
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void MipsRegisterInfo::
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emitPrologue(MachineFunction &MF) const
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{
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
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// Replace the dummy '0' SPOffset by the negative
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// offsets, as explained on LowerFORMAL_ARGUMENTS
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MipsFI->adjustLoadArgsFI(MFI);
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MipsFI->adjustStoreVarArgsFI(MFI);
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// Get the number of bytes to allocate from the FrameInfo.
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int NumBytes = (int) MFI->getStackSize();
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#ifndef NDEBUG
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DOUT << "\n<--- EMIT PROLOGUE --->\n";
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DOUT << "Actual Stack size :" << NumBytes << "\n";
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#endif
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// No need to allocate space on the stack.
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if (NumBytes == 0) return;
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int FPOffset, RAOffset;
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// Allocate space for saved RA and FP when needed
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if ((hasFP(MF)) && (MFI->hasCalls())) {
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FPOffset = NumBytes;
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RAOffset = (NumBytes+4);
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NumBytes += 8;
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} else if ((!hasFP(MF)) && (MFI->hasCalls())) {
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FPOffset = 0;
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RAOffset = NumBytes;
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NumBytes += 4;
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} else if ((hasFP(MF)) && (!MFI->hasCalls())) {
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FPOffset = NumBytes;
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RAOffset = 0;
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NumBytes += 4;
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}
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MFI->setObjectOffset(MFI->CreateStackObject(4,4), FPOffset);
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MFI->setObjectOffset(MFI->CreateStackObject(4,4), RAOffset);
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MipsFI->setFPStackOffset(FPOffset);
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MipsFI->setRAStackOffset(RAOffset);
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// Align stack.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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NumBytes = ((NumBytes+Align-1)/Align*Align);
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#ifndef NDEBUG
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DOUT << "FPOffset :" << FPOffset << "\n";
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DOUT << "RAOffset :" << RAOffset << "\n";
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DOUT << "New stack size :" << NumBytes << "\n\n";
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#endif
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// Update frame info
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MFI->setStackSize(NumBytes);
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// PIC speficic function prologue
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if (isPIC)
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BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(Mips::T9);
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// Adjust stack : addi sp, sp, (-imm)
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BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
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.addReg(Mips::SP).addImm(-NumBytes);
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// Save the return address only if the function isnt a leaf one.
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// sw $ra, stack_loc($sp)
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if (MFI->hasCalls()) {
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BuildMI(MBB, MBBI, TII.get(Mips::SW))
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.addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
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}
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// if framepointer enabled, save it and set it
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// to point to the stack pointer
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if (hasFP(MF)) {
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// sw $fp,stack_loc($sp)
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BuildMI(MBB, MBBI, TII.get(Mips::SW))
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.addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
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// move $fp, $sp
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BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
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.addReg(Mips::SP).addReg(Mips::ZERO);
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}
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// PIC speficic function prologue
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if ((isPIC) && (MFI->hasCalls()))
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BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
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.addImm(MipsFI->getGPStackOffset());
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}
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void MipsRegisterInfo::
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emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
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{
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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// Get the number of bytes from FrameInfo
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int NumBytes = (int) MFI->getStackSize();
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// Get the FI's where RA and FP are saved.
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int FPOffset = MipsFI->getFPStackOffset();
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int RAOffset = MipsFI->getRAStackOffset();
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// if framepointer enabled, restore it and restore the
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// stack pointer
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if (hasFP(MF)) {
|
|
// move $sp, $fp
|
|
BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
|
|
.addReg(Mips::FP).addReg(Mips::ZERO);
|
|
|
|
// lw $fp,stack_loc($sp)
|
|
BuildMI(MBB, MBBI, TII.get(Mips::LW))
|
|
.addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
|
|
}
|
|
|
|
// Restore the return address only if the function isnt a leaf one.
|
|
// lw $ra, stack_loc($sp)
|
|
if (MFI->hasCalls()) {
|
|
BuildMI(MBB, MBBI, TII.get(Mips::LW))
|
|
.addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
|
|
}
|
|
|
|
// adjust stack : insert addi sp, sp, (imm)
|
|
if (NumBytes) {
|
|
BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
|
|
.addReg(Mips::SP).addImm(NumBytes);
|
|
}
|
|
}
|
|
|
|
void MipsRegisterInfo::
|
|
processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
|
|
// Set the SPOffset on the FI where GP must be saved/loaded.
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
if (MFI->hasCalls()) {
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
#ifndef NDEBUG
|
|
DOUT << "processFunctionBeforeFrameFinalized\n";
|
|
DOUT << "GPOffset :" << MipsFI->getGPStackOffset() << "\n";
|
|
DOUT << "FI :" << MipsFI->getGPFI() << "\n";
|
|
#endif
|
|
MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
|
|
}
|
|
}
|
|
|
|
unsigned MipsRegisterInfo::
|
|
getRARegister() const {
|
|
return Mips::RA;
|
|
}
|
|
|
|
unsigned MipsRegisterInfo::
|
|
getFrameRegister(MachineFunction &MF) const {
|
|
return hasFP(MF) ? Mips::FP : Mips::SP;
|
|
}
|
|
|
|
unsigned MipsRegisterInfo::
|
|
getEHExceptionRegister() const {
|
|
assert(0 && "What is the exception register");
|
|
return 0;
|
|
}
|
|
|
|
unsigned MipsRegisterInfo::
|
|
getEHHandlerRegister() const {
|
|
assert(0 && "What is the exception handler register");
|
|
return 0;
|
|
}
|
|
|
|
int MipsRegisterInfo::
|
|
getDwarfRegNum(unsigned RegNum, bool isEH) const {
|
|
assert(0 && "What is the dwarf register number");
|
|
return -1;
|
|
}
|
|
|
|
#include "MipsGenRegisterInfo.inc"
|
|
|