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d64b5c82b9
the stored register is killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
110 lines
3.9 KiB
C++
110 lines
3.9 KiB
C++
//===- MipsRegisterInfo.h - Mips Register Information Impl ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Bruno Cardoso Lopes and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSREGISTERINFO_H
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#define MIPSREGISTERINFO_H
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#include "llvm/Target/MRegisterInfo.h"
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#include "MipsGenRegisterInfo.h.inc"
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namespace llvm {
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class TargetInstrInfo;
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class Type;
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struct MipsRegisterInfo : public MipsGenRegisterInfo {
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const TargetInstrInfo &TII;
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MipsRegisterInfo(const TargetInstrInfo &tii);
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// Mips::RA, return the number that it corresponds to (e.g. 31).
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static unsigned getRegisterNumbering(unsigned RegEnum);
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/// Code Generation virtual methods...
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC) const;
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void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, const MachineInstr *Orig) const;
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MachineInstr* foldMemoryOperand(MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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MachineInstr* foldMemoryOperand(MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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return 0;
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}
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void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const;
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const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
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const TargetRegisterClass* const*
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getCalleeSavedRegClasses(const MachineFunction* MF = 0) const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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/// Stack Frame Processing Methods
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS = NULL) const;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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/// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(MachineFunction &MF) const;
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/// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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};
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} // end namespace llvm
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#endif
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