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https://github.com/c64scene-ar/llvm-6502.git
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98b419bff7
Summary: This patch also fixes an issue with the way the Mips assembler enables/disables architecture features. Before this patch, the assembler never disabled feature bits. For example, .set mips64 .set mips32r2 would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right. Unfortunately this isn't trivial to fix because there's not an easy way to clear feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits that imply the feature being cleared and not the implied bits by the feature (there's a better explanation to the code I added). Patch by Matheus Almeida and updated by Toma Tabacu Reviewers: vmedic, matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu, llvm-commits Differential Revision: http://reviews.llvm.org/D4123 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214709 91177308-0d34-0410-b5e6-96231b3b80d8
52 lines
1.1 KiB
ArmAsm
52 lines
1.1 KiB
ArmAsm
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips1 | \
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# RUN: FileCheck %s
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.text
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.set noreorder
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.set mips1
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add $2, $2, $2
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.set mips2
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ll $2,-2($2)
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.set mips3
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dadd $2,$2,$2
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.set mips4
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ldxc1 $f8,$2($4)
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.set mips5
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luxc1 $f19,$2($4)
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.set mips32
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clo $2,$2
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.set mips32r2
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rotr $2,15
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.set mips32r6
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mod $2, $4, $6
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.set mips64
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daddi $2, $2, 10
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.set mips64r2
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drotr32 $1,$14,15
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.set mips64r6
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mod $2, $4, $6
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# CHECK: .set noreorder
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# CHECK: .set mips1
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# CHECK: add $2, $2, $2
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# CHECK: .set mips2
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# CHECK: ll $2, -2($2)
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# CHECK: .set mips3
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# CHECK: dadd $2, $2, $2
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# CHECK: .set mips4
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# CHECK: ldxc1 $f8, $2($4)
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# CHECK: .set mips5
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# CHECK: luxc1 $f19, $2($4)
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# CHECK: .set mips32
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# CHECK: clo $2, $2
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# CHECK: .set mips32r2
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# CHECK: rotr $2, $2, 15
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# CHECK: .set mips32r6
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# CHECK: mod $2, $4, $6
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# CHECK: .set mips64
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# CHECK: daddi $2, $2, 10
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# CHECK: .set mips64r2
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# CHECK: drotr32 $1, $14, 15
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# CHECK: .set mips64r6
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# CHECK: mod $2, $4, $6
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