mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-09 10:05:41 +00:00
8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
185 lines
7.7 KiB
LLVM
185 lines
7.7 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s
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;EG-CHECK-LABEL: {{^}}ashr_v2i32:
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;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK-LABEL: {{^}}ashr_v2i32:
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;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32> addrspace(1) * %in
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%b = load <2 x i32> addrspace(1) * %b_ptr
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%result = ashr <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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;EG-CHECK-LABEL: {{^}}ashr_v4i32:
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;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK-LABEL: {{^}}ashr_v4i32:
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;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32> addrspace(1) * %in
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%b = load <4 x i32> addrspace(1) * %b_ptr
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%result = ashr <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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;EG-CHECK-LABEL: {{^}}ashr_i64:
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;EG-CHECK: ASHR
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;SI-CHECK-LABEL: {{^}}ashr_i64:
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;SI-CHECK: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8
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define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) {
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entry:
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%0 = sext i32 %in to i64
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%1 = ashr i64 %0, 8
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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;EG-CHECK-LABEL: {{^}}ashr_i64_2:
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;EG-CHECK: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
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;EG-CHECK: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
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;EG-CHECK: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
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;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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;EG-CHECK-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
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;EG-CHECK-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
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;EG-CHECK-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
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;EG-CHECK-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
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;EG-CHECK-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
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;EG-CHECK-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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;SI-CHECK-LABEL: {{^}}ashr_i64_2:
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;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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entry:
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%b_ptr = getelementptr i64 addrspace(1)* %in, i64 1
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%a = load i64 addrspace(1) * %in
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%b = load i64 addrspace(1) * %b_ptr
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%result = ashr i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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;EG-CHECK-LABEL: {{^}}ashr_v2i64:
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;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
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;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
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;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]]
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;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]]
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;EG-CHECK-DAG: LSHL {{.*}}, 1
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;EG-CHECK-DAG: LSHL {{.*}}, 1
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;EG-CHECK-DAG: ASHR {{.*}}, [[SHA]]
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;EG-CHECK-DAG: ASHR {{.*}}, [[SHB]]
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;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
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;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
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;EG-CHECK-DAG: OR_INT
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;EG-CHECK-DAG: OR_INT
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;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-CHECK-DAG: ASHR
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;EG-CHECK-DAG: ASHR
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;EG-CHECK-DAG: ASHR {{.*}}, literal
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;EG-CHECK-DAG: ASHR {{.*}}, literal
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;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
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;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
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;EG-CHECK-DAG: CNDE_INT
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;EG-CHECK-DAG: CNDE_INT
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;EG-CHECK-DAG: CNDE_INT
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;EG-CHECK-DAG: CNDE_INT
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;SI-CHECK-LABEL: {{^}}ashr_v2i64:
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;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1
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%a = load <2 x i64> addrspace(1) * %in
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%b = load <2 x i64> addrspace(1) * %b_ptr
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%result = ashr <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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;EG-CHECK-LABEL: {{^}}ashr_v4i64:
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;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
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;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
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;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
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;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
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;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]]
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;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]]
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;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHC]]
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;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHD]]
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;EG-CHECK-DAG: LSHL {{.*}}, 1
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;EG-CHECK-DAG: LSHL {{.*}}, 1
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;EG-CHECK-DAG: LSHL {{.*}}, 1
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;EG-CHECK-DAG: LSHL {{.*}}, 1
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;EG-CHECK-DAG: ASHR {{.*}}, [[SHA]]
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;EG-CHECK-DAG: ASHR {{.*}}, [[SHB]]
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;EG-CHECK-DAG: ASHR {{.*}}, [[SHC]]
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;EG-CHECK-DAG: ASHR {{.*}}, [[SHD]]
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;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
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;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
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;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]
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;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]
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;EG-CHECK-DAG: OR_INT
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;EG-CHECK-DAG: OR_INT
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;EG-CHECK-DAG: OR_INT
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;EG-CHECK-DAG: OR_INT
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;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-CHECK-DAG: ASHR
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;EG-CHECK-DAG: ASHR
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;EG-CHECK-DAG: ASHR
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;EG-CHECK-DAG: ASHR
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;EG-CHECK-DAG: ASHR {{.*}}, literal
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;EG-CHECK-DAG: ASHR {{.*}}, literal
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;EG-CHECK-DAG: ASHR {{.*}}, literal
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;EG-CHECK-DAG: ASHR {{.*}}, literal
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;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
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;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
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;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
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;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
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;EG-CHECK-DAG: CNDE_INT
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;EG-CHECK-DAG: CNDE_INT
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;EG-CHECK-DAG: CNDE_INT
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;EG-CHECK-DAG: CNDE_INT
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;EG-CHECK-DAG: CNDE_INT
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;EG-CHECK-DAG: CNDE_INT
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;EG-CHECK-DAG: CNDE_INT
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;EG-CHECK-DAG: CNDE_INT
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;SI-CHECK-LABEL: {{^}}ashr_v4i64:
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;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1
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%a = load <4 x i64> addrspace(1) * %in
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%b = load <4 x i64> addrspace(1) * %b_ptr
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%result = ashr <4 x i64> %a, %b
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store <4 x i64> %result, <4 x i64> addrspace(1)* %out
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ret void
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}
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