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https://github.com/c64scene-ar/llvm-6502.git
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64aa0ea4e9
whimper out of doing things the Right Way, and hack up a generic 'BRCALL' instruction, that gets generated when calls are lowered. This gets selected by hand in the DAG isel, where it gets turned into real (i.e. in tablegen) br.call instructions. BUG: this dies on void calls, but seems to work otherwise? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24952 91177308-0d34-0410-b5e6-96231b3b80d8
96 lines
3.6 KiB
C++
96 lines
3.6 KiB
C++
//===-- IA64ISelLowering.h - IA64 DAG Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Duraid Madina and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that IA64 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_IA64_IA64ISELLOWERING_H
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#define LLVM_TARGET_IA64_IA64ISELLOWERING_H
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "IA64.h"
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namespace llvm {
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namespace IA64ISD {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+IA64::INSTRUCTION_LIST_END,
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/// FSEL - Traditional three-operand fsel node.
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///
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FSEL,
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/// FCFID - The FCFID instruction, taking an f64 operand and producing
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/// and f64 value containing the FP representation of the integer that
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/// was temporarily in the f64 operand.
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FCFID,
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/// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
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/// operand, producing an f64 value containing the integer representation
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/// of that FP value.
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FCTIDZ, FCTIWZ,
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/// GETFD - the getf.d instruction takes a floating point operand and
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/// returns its 64-bit memory representation as an i64
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GETFD,
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// TODO: explain this hack
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BRCALL
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};
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}
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class IA64TargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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//int ReturnAddrIndex; // FrameIndex for return slot.
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unsigned GP, SP, RP; // FIXME - clean this mess up
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public:
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IA64TargetLowering(TargetMachine &TM);
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unsigned VirtGPR; // this is public so it can be accessed in the selector
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// for ISD::RET. add an accessor instead? FIXME
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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// XXX virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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/// LowerArguments - This hook must be implemented to indicate how we should
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/// lower the arguments for the specified function, into the specified DAG.
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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/// LowerCallTo - This hook lowers an abstract call to a function into an
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/// actual call.
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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unsigned CC,
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bool isTailCall, SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG);
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virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG);
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virtual std::pair<SDOperand,SDOperand>
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LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG);
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// XXX virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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// XXX MachineBasicBlock *MBB);
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};
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}
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#endif // LLVM_TARGET_IA64_IA64ISELLOWERING_H
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