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c9c8b2a804
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). <rant>DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen.</rant> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
24 lines
709 B
LLVM
24 lines
709 B
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep fceq %t1.s | count 1
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; RUN: grep fcmeq %t1.s | count 1
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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; Exercise the floating point comparison operators for f32:
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declare double @fabs(double)
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declare float @fabsf(float)
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define i1 @fcmp_eq(float %arg1, float %arg2) {
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%A = fcmp oeq float %arg1, %arg2
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ret i1 %A
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}
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define i1 @fcmp_mag_eq(float %arg1, float %arg2) {
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%1 = call float @fabsf(float %arg1)
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%2 = call float @fabsf(float %arg2)
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%3 = fcmp oeq float %1, %2
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ret i1 %3
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}
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