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de33227462
move from and to coprocessors 0 and 2. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
378 lines
10 KiB
TableGen
378 lines
10 KiB
TableGen
//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Describe MIPS instructions format
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//
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// CPU INSTRUCTION FORMATS
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//
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// opcode - operation code.
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// rs - src reg.
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// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
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// rd - dst reg, only used on 3 regs instr.
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// shamt - only used on shift instructions, contains the shift amount.
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// funct - combined with opcode field give us an operation code.
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//
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//===----------------------------------------------------------------------===//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<4> val> {
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bits<4> Value = val;
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}
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def Pseudo : Format<0>;
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def FrmR : Format<1>;
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def FrmI : Format<2>;
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def FrmJ : Format<3>;
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def FrmFR : Format<4>;
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def FrmFI : Format<5>;
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def FrmOther : Format<6>; // Instruction w/ a custom format
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// Generic Mips Format
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class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format f>: Instruction
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{
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field bits<32> Inst;
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Format Form = f;
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let Namespace = "Mips";
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let Size = 4;
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bits<6> Opcode = 0;
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// Top 6 bits are the 'opcode' field
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let Inst{31-26} = Opcode;
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Itinerary = itin;
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//
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// Attributes specific to Mips instructions...
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//
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bits<4> FormBits = Form.Value;
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// TSFlags layout should be kept in sync with MipsInstrInfo.h.
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let TSFlags{3-0} = FormBits;
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let DecoderNamespace = "Mips";
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field bits<32> SoftFail = 0;
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}
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// Mips32/64 Instruction Format
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class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format f>:
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MipsInst<outs, ins, asmstr, pattern, itin, f> {
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let Predicates = [HasStandardEncoding];
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}
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// Mips Pseudo Instructions Format
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class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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// Mips32/64 Pseudo Instruction Format
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class PseudoSE<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsPseudo<outs, ins, asmstr, pattern> {
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let Predicates = [HasStandardEncoding];
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}
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// Pseudo-instructions for alternate assembly syntax (never used by codegen).
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// These are aliases that require C++ handling to convert to the target
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// instruction, while InstAliases can be handled directly by tblgen.
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class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
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MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
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let isPseudo = 1;
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let Pattern = [];
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}
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//===----------------------------------------------------------------------===//
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// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
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//===----------------------------------------------------------------------===//
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class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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InstSE<outs, ins, asmstr, pattern, itin, FrmR>
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{
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<5> shamt;
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bits<6> funct;
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let Opcode = op;
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let funct = _funct;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = shamt;
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let Inst{5-0} = funct;
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}
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//===----------------------------------------------------------------------===//
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// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
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//===----------------------------------------------------------------------===//
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class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
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{
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bits<5> rt;
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bits<5> rs;
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bits<16> imm16;
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let Opcode = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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InstSE<outs, ins, asmstr, pattern, itin, FrmI>
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{
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bits<5> rs;
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bits<5> rt;
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bits<16> imm16;
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let Opcode = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = imm16;
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}
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//===----------------------------------------------------------------------===//
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// Format J instruction class in Mips : <|opcode|address|>
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//===----------------------------------------------------------------------===//
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class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmJ>
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{
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bits<26> addr;
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let Opcode = op;
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let Inst{25-0} = addr;
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}
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//===----------------------------------------------------------------------===//
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// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
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//===----------------------------------------------------------------------===//
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class MFC3OP<bits<6> op, bits<5> _mfmt, dag outs, dag ins, string asmstr>:
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InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>
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{
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bits<5> mfmt;
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bits<5> rt;
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bits<5> rd;
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bits<3> sel;
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let Opcode = op;
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let mfmt = _mfmt;
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let Inst{25-21} = mfmt;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-3} = 0;
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let Inst{2-0} = sel;
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}
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//===----------------------------------------------------------------------===//
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//
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// FLOATING POINT INSTRUCTION FORMATS
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//
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// opcode - operation code.
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// fs - src reg.
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// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
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// fd - dst reg, only used on 3 regs instr.
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// fmt - double or single precision.
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// funct - combined with opcode field give us an operation code.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
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//===----------------------------------------------------------------------===//
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class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
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string asmstr, list<dag> pattern> :
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InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFR>
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{
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bits<5> fd;
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bits<5> fs;
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bits<5> ft;
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bits<5> fmt;
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bits<6> funct;
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let Opcode = op;
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let funct = _funct;
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let fmt = _fmt;
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let Inst{25-21} = fmt;
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let Inst{20-16} = ft;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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//===----------------------------------------------------------------------===//
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// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
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//===----------------------------------------------------------------------===//
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class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
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InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
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{
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bits<5> ft;
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bits<5> base;
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bits<16> imm16;
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let Opcode = op;
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let Inst{25-21} = base;
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let Inst{20-16} = ft;
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let Inst{15-0} = imm16;
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}
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//===----------------------------------------------------------------------===//
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// Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
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//===----------------------------------------------------------------------===//
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class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
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InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
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{
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bits<5> fs;
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bits<5> ft;
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bits<4> cc;
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bits<5> fmt;
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let Opcode = 0x11;
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let fmt = _fmt;
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let Inst{25-21} = fmt;
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let Inst{20-16} = ft;
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let Inst{15-11} = fs;
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let Inst{10-6} = 0;
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let Inst{5-4} = 0b11;
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let Inst{3-0} = cc;
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}
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class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr,
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list<dag> pattern> :
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InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
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{
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bits<5> rd;
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bits<5> rs;
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bits<3> cc;
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bits<1> tf;
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let Opcode = 0;
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let tf = _tf;
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let Inst{25-21} = rs;
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let Inst{20-18} = cc;
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let Inst{17} = 0;
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let Inst{16} = tf;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = 1;
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}
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class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
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list<dag> pattern> :
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InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
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{
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bits<5> fd;
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bits<5> fs;
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bits<3> cc;
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bits<5> fmt;
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bits<1> tf;
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let Opcode = 17;
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let fmt = _fmt;
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let tf = _tf;
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let Inst{25-21} = fmt;
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let Inst{20-18} = cc;
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let Inst{17} = 0;
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let Inst{16} = tf;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = 17;
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}
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// FP unary instructions without patterns.
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class FFR1<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
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RegisterClass DstRC, RegisterClass SrcRC> :
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FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
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!strconcat(opstr, ".", fmtstr, "\t$fd, $fs"), []> {
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let ft = 0;
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}
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// FP unary instructions with patterns.
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class FFR1P<bits<6> funct, bits<5> fmt, string opstr, string fmtstr,
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RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
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FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
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!strconcat(opstr, ".", fmtstr, "\t$fd, $fs"),
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[(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
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let ft = 0;
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}
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class FFR2P<bits<6> funct, bits<5> fmt, string opstr,
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string fmtstr, RegisterClass RC, SDNode OpNode> :
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FFR<0x11, funct, fmt, (outs RC:$fd), (ins RC:$fs, RC:$ft),
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!strconcat(opstr, ".", fmtstr, "\t$fd, $fs, $ft"),
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[(set RC:$fd, (OpNode RC:$fs, RC:$ft))]>;
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// Floating point madd/msub/nmadd/nmsub.
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class FFMADDSUB<bits<3> funct, bits<3> fmt, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther> {
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bits<5> fd;
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bits<5> fr;
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bits<5> fs;
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bits<5> ft;
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let Opcode = 0x13;
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let Inst{25-21} = fr;
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let Inst{20-16} = ft;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-3} = funct;
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let Inst{2-0} = fmt;
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}
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// FP indexed load/store instructions.
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class FFMemIdx<bits<6> funct, dag outs, dag ins, string asmstr,
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list<dag> pattern> :
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InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
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{
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bits<5> base;
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bits<5> index;
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bits<5> fs;
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bits<5> fd;
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let Opcode = 0x13;
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let Inst{25-21} = base;
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let Inst{20-16} = index;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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