mirror of
https://github.com/c64scene-ar/llvm-6502.git
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It's completely unnecessary and can be replace with proper SReg_64 handling instead. This actually fixes a piglit test on SI. v2: use correct register class in addRegisterClass, set special classes as not allocatable v3: revert setting special classes as not allocateable This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175355 91177308-0d34-0410-b5e6-96231b3b80d8
189 lines
6.3 KiB
TableGen
189 lines
6.3 KiB
TableGen
//===-- SIInstrFormats.td - SI Instruction Formats ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// SI Instruction format definitions.
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//
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// Instructions with _32 take 32-bit operands.
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// Instructions with _64 take 64-bit operands.
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//
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// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
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// encoding is the standard encoding, but instruction that make use of
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// any of the instruction modifiers must use the 64-bit encoding.
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//
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// Instructions with _e32 use the 32-bit encoding.
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// Instructions with _e64 use the 64-bit encoding.
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//
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//===----------------------------------------------------------------------===//
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class VOP3_32 <bits<9> op, string opName, list<dag> pattern>
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: VOP3 <op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
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class VOP3_64 <bits<9> op, string opName, list<dag> pattern>
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: VOP3 <op, (outs VReg_64:$dst), (ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
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class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
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: SOP1 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0), opName, pattern>;
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class SOP1_64 <bits<8> op, string opName, list<dag> pattern>
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: SOP1 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0), opName, pattern>;
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class SOP2_32 <bits<7> op, string opName, list<dag> pattern>
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: SOP2 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>;
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class SOP2_64 <bits<7> op, string opName, list<dag> pattern>
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: SOP2 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>;
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class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> :
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VOP1 <
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op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
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>;
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multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
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def _e32: VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>;
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def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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}
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multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> {
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def _e32 : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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def _e64 : VOP3_64 <
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{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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}
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class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> :
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VOP2 <
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op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
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>;
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multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
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def _e32 : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>;
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def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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}
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multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> {
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def _e32: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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def _e64 : VOP3_64 <
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{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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}
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class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
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: SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
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class SOPK_64 <bits<5> op, string opName, list<dag> pattern>
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: SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
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multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> {
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def _e32 : VOPC <op, (ins arc:$src0, vrc:$src1), opName, pattern>;
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def _e64 : VOP3 <
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{0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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(outs SReg_64:$dst),
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(ins arc:$src0, vrc:$src1,
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InstFlag:$abs, InstFlag:$clamp,
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InstFlag:$omod, InstFlag:$neg),
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opName, pattern
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> {
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let SRC2 = 0x80;
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}
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}
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multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern>
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: VOPC_Helper <op, VReg_32, VSrc_32, opName, pattern>;
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multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern>
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: VOPC_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
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: SOPC <op, (outs SCCReg:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>;
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class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
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: SOPC <op, (outs SCCReg:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>;
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class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
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op,
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(outs VReg_128:$vdata),
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(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
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GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
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asm,
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[]> {
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let mayLoad = 1;
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let mayStore = 0;
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}
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class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
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op,
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(outs),
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(ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
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i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
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GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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asm,
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[]> {
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let mayStore = 1;
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let mayLoad = 0;
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}
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class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
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op,
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(outs regClass:$dst),
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(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
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i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
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i1imm:$tfe, SSrc_32:$soffset),
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asm,
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[]> {
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let mayLoad = 1;
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let mayStore = 0;
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}
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class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
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op,
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(outs regClass:$dst),
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(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
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i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
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i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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asm,
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[]> {
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let mayLoad = 1;
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let mayStore = 0;
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}
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multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
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def _IMM : SMRD <
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op, 1,
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(outs dstClass:$dst),
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(ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
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asm,
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[]
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>;
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def _SGPR : SMRD <
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op, 0,
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(outs dstClass:$dst),
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(ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
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asm,
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[]
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>;
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}
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