Tim Northover c5cc2e1a5a AArch64: make inexact signalling on round Darwin-specific ... C11 leaves the choice on whether round-to-integer operations set the inexact flag implementation-defined. Darwin does expect it to be set, but this seems to be against the intent of the IEEE document and slower to implement anyway. So it should be opt-in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242446 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-16 21:30:21 +00:00
..
AsmParser
Disassembler
InstPrinter
MCTargetDesc	MC: Remove MCSubtargetInfo() default constructor	2015-07-10 22:43:42 +00:00
TargetInfo
Utils
AArch64.h
AArch64.td
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp	MachineRegisterInfo: Remove UsedPhysReg infrastructure	2015-07-14 17:52:07 +00:00
AArch64AddressTypePromotion.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp
AArch64BranchRelaxation.cpp
AArch64CallingConvention.h	Move most user of TargetMachine::getDataLayout to the Module one	2015-07-16 06:11:10 +00:00
AArch64CallingConvention.td	Move most user of TargetMachine::getDataLayout to the Module one	2015-07-16 06:11:10 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp
AArch64FastISel.cpp	Make TargetLowering::getPointerTy() taking DataLayout as an argument	2015-07-09 02:09:04 +00:00
AArch64FrameLowering.cpp	Move most user of TargetMachine::getDataLayout to the Module one	2015-07-16 06:11:10 +00:00
AArch64FrameLowering.h	PrologEpilogInserter: Rewrite API to determine callee save regsiters.	2015-07-14 17:17:13 +00:00
AArch64InstrAtomics.td
AArch64InstrFormats.td	AArch64: Implement conditional compare sequence matching.	2015-07-16 20:02:37 +00:00
AArch64InstrInfo.cpp
AArch64InstrInfo.h
AArch64InstrInfo.td	AArch64: Implement conditional compare sequence matching.	2015-07-16 20:02:37 +00:00
AArch64ISelDAGToDAG.cpp	AArch64: make inexact signalling on round Darwin-specific	2015-07-16 21:30:21 +00:00
AArch64ISelLowering.cpp	AArch64: Implement conditional compare sequence matching.	2015-07-16 20:02:37 +00:00
AArch64ISelLowering.h	AArch64: Implement conditional compare sequence matching.	2015-07-16 20:02:37 +00:00
AArch64LoadStoreOptimizer.cpp
AArch64MachineCombinerPattern.h
AArch64MachineFunctionInfo.h	WebAssembly: fix build breakage.	2015-07-14 23:06:07 +00:00
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RegisterInfo.cpp	Target RegisterInfo: devirtualize TargetFrameLowering	2015-07-10 18:13:17 +00:00
AArch64RegisterInfo.h
AArch64RegisterInfo.td
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td	[AArch64] Refines the Cortex-A57 Machine Model	2014-09-29 21:27:36 +00:00
AArch64SchedCyclone.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp	Remove getDataLayout() from TargetSelectionDAGInfo (had no users)	2015-07-09 02:10:08 +00:00
AArch64SelectionDAGInfo.h	Remove getDataLayout() from TargetSelectionDAGInfo (had no users)	2015-07-09 02:10:08 +00:00
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp	Remove getDataLayout() from TargetSelectionDAGInfo (had no users)	2015-07-09 02:10:08 +00:00
AArch64Subtarget.h
AArch64TargetMachine.cpp
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp	Remove getDataLayout() from TargetLowering	2015-07-09 02:09:52 +00:00
AArch64TargetTransformInfo.h	Make TargetTransformInfo keeping a reference to the Module DataLayout	2015-07-09 02:08:42 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile