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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22523 91177308-0d34-0410-b5e6-96231b3b80d8
871 lines
30 KiB
C++
871 lines
30 KiB
C++
//===-- MSchedGraphSB.cpp - Scheduling Graph ----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// A graph class for dependencies. This graph only contains true, anti, and
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// output data dependencies for a given MachineBasicBlock. Dependencies
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// across iterations are also computed. Unless data dependence analysis
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// is provided, a conservative approach of adding dependencies between all
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// loads and stores is taken.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "ModuloSchedSB"
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#include "MSchedGraphSB.h"
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#include "../SparcV9RegisterInfo.h"
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#include "../MachineCodeForInstruction.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/Constants.h"
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#include "llvm/Instructions.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include <cstdlib>
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#include <algorithm>
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#include <set>
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#include "llvm/Target/TargetSchedInfo.h"
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#include "../SparcV9Internals.h"
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using namespace llvm;
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//MSchedGraphSBNode constructor
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MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst,
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MSchedGraphSB *graph, unsigned idx,
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unsigned late, bool isBranch)
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: Inst(inst), Parent(graph), index(idx), latency(late),
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isBranchInstr(isBranch) {
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//Add to the graph
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graph->addNode(inst, this);
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}
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//MSchedGraphSBNode constructor
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MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst,
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std::vector<const MachineInstr*> &other,
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MSchedGraphSB *graph, unsigned idx,
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unsigned late, bool isPNode)
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: Inst(inst), otherInstrs(other), Parent(graph), index(idx), latency(late), isPredicateNode(isPNode) {
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isBranchInstr = false;
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//Add to the graph
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graph->addNode(inst, this);
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}
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//MSchedGraphSBNode copy constructor
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MSchedGraphSBNode::MSchedGraphSBNode(const MSchedGraphSBNode &N)
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: Predecessors(N.Predecessors), Successors(N.Successors) {
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Inst = N.Inst;
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Parent = N.Parent;
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index = N.index;
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latency = N.latency;
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isBranchInstr = N.isBranchInstr;
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otherInstrs = N.otherInstrs;
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}
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//Print the node (instruction and latency)
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void MSchedGraphSBNode::print(std::ostream &os) const {
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if(!isPredicate())
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os << "MSchedGraphSBNode: Inst=" << *Inst << ", latency= " << latency << "\n";
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else
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os << "Pred Node\n";
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}
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//Get the edge from a predecessor to this node
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MSchedGraphSBEdge MSchedGraphSBNode::getInEdge(MSchedGraphSBNode *pred) {
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//Loop over all the successors of our predecessor
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//return the edge the corresponds to this in edge
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for (MSchedGraphSBNode::succ_iterator I = pred->succ_begin(),
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E = pred->succ_end(); I != E; ++I) {
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if (*I == this)
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return I.getEdge();
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}
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assert(0 && "Should have found edge between this node and its predecessor!");
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abort();
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}
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//Get the iteration difference for the edge from this node to its successor
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unsigned MSchedGraphSBNode::getIteDiff(MSchedGraphSBNode *succ) {
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for(std::vector<MSchedGraphSBEdge>::iterator I = Successors.begin(),
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E = Successors.end();
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I != E; ++I) {
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if(I->getDest() == succ)
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return I->getIteDiff();
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}
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return 0;
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}
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//Get the index into the vector of edges for the edge from pred to this node
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unsigned MSchedGraphSBNode::getInEdgeNum(MSchedGraphSBNode *pred) {
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//Loop over all the successors of our predecessor
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//return the edge the corresponds to this in edge
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int count = 0;
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for(MSchedGraphSBNode::succ_iterator I = pred->succ_begin(),
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E = pred->succ_end();
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I != E; ++I) {
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if(*I == this)
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return count;
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count++;
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}
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assert(0 && "Should have found edge between this node and its predecessor!");
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abort();
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}
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//Determine if succ is a successor of this node
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bool MSchedGraphSBNode::isSuccessor(MSchedGraphSBNode *succ) {
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for(succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
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if(*I == succ)
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return true;
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return false;
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}
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//Dtermine if pred is a predecessor of this node
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bool MSchedGraphSBNode::isPredecessor(MSchedGraphSBNode *pred) {
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if(std::find( Predecessors.begin(), Predecessors.end(),
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pred) != Predecessors.end())
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return true;
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else
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return false;
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}
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//Add a node to the graph
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void MSchedGraphSB::addNode(const MachineInstr* MI,
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MSchedGraphSBNode *node) {
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//Make sure node does not already exist
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assert(GraphMap.find(MI) == GraphMap.end()
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&& "New MSchedGraphSBNode already exists for this instruction");
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GraphMap[MI] = node;
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}
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//Delete a node to the graph
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void MSchedGraphSB::deleteNode(MSchedGraphSBNode *node) {
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//Delete the edge to this node from all predecessors
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while(node->pred_size() > 0) {
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//DEBUG(std::cerr << "Delete edge from: " << **P << " to " << *node << "\n");
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MSchedGraphSBNode *pred = *(node->pred_begin());
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pred->deleteSuccessor(node);
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}
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//Remove this node from the graph
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GraphMap.erase(node->getInst());
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}
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//Create a graph for a machine block. The ignoreInstrs map is so that
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//we ignore instructions associated to the index variable since this
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//is a special case in Modulo Scheduling. We only want to deal with
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//the body of the loop.
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MSchedGraphSB::MSchedGraphSB(std::vector<const MachineBasicBlock*> &bbs,
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const TargetMachine &targ,
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std::map<const MachineInstr*, unsigned> &ignoreInstrs,
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DependenceAnalyzer &DA,
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std::map<MachineInstr*, Instruction*> &machineTollvm)
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: BBs(bbs), Target(targ) {
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//Make sure there is at least one BB and it is not null,
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assert(((bbs.size() >= 1) && bbs[1] != NULL) && "Basic Block is null");
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std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > liveOutsideTrace;
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std::set<const BasicBlock*> llvmBBs;
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for(std::vector<const MachineBasicBlock*>::iterator MBB = bbs.begin(), ME = bbs.end()-1;
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MBB != ME; ++MBB)
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llvmBBs.insert((*MBB)->getBasicBlock());
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//create predicate nodes
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DEBUG(std::cerr << "Create predicate nodes\n");
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for(std::vector<const MachineBasicBlock*>::iterator MBB = bbs.begin(), ME = bbs.end()-1;
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MBB != ME; ++MBB) {
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//Get LLVM basic block
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BasicBlock *BB = (BasicBlock*) (*MBB)->getBasicBlock();
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//Get Terminator
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BranchInst *b = dyn_cast<BranchInst>(BB->getTerminator());
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std::vector<const MachineInstr*> otherInstrs;
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MachineInstr *instr = 0;
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//Get the condition for the branch (we already checked if it was conditional)
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if(b->isConditional()) {
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Value *cond = b->getCondition();
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DEBUG(std::cerr << "Condition: " << *cond << "\n");
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assert(cond && "Condition must not be null!");
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if(Instruction *I = dyn_cast<Instruction>(cond)) {
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
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if(tempMvec.size() > 0) {
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DEBUG(std::cerr << *(tempMvec[tempMvec.size()-1]) << "\n");;
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instr = (MachineInstr*) tempMvec[tempMvec.size()-1];
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}
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}
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}
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//Get Machine target information for calculating latency
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const TargetInstrInfo *MTI = Target.getInstrInfo();
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MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(b);
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int offset = tempMvec.size();
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for (unsigned j = 0; j < tempMvec.size(); j++) {
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MachineInstr *mi = tempMvec[j];
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if(MTI->isNop(mi->getOpcode()))
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continue;
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if(!instr) {
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instr = mi;
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DEBUG(std::cerr << "No Cond MI: " << *mi << "\n");
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}
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else {
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DEBUG(std::cerr << *mi << "\n");;
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otherInstrs.push_back(mi);
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}
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}
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//Node is created and added to the graph automatically
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MSchedGraphSBNode *node = new MSchedGraphSBNode(instr, otherInstrs, this, (*MBB)->size()-offset-1, 3, true);
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DEBUG(std::cerr << "Created Node: " << *node << "\n");
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//Now loop over all instructions and see if their def is live outside the trace
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MachineBasicBlock *mb = (MachineBasicBlock*) *MBB;
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for(MachineBasicBlock::iterator I = mb->begin(), E = mb->end(); I != E; ++I) {
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MachineInstr *instr = I;
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if(MTI->isNop(instr->getOpcode()) || MTI->isBranch(instr->getOpcode()))
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continue;
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if(node->getInst() == instr)
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continue;
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for(unsigned i=0; i < instr->getNumOperands(); ++i) {
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MachineOperand &mOp = instr->getOperand(i);
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if(mOp.isDef() && mOp.getType() == MachineOperand::MO_VirtualRegister) {
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Value *val = mOp.getVRegValue();
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//Check if there is a use not in the trace
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for(Value::use_iterator V = val->use_begin(), VE = val->use_end(); V != VE; ++V) {
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if (Instruction *Inst = dyn_cast<Instruction>(*V)) {
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if(llvmBBs.count(Inst->getParent()))
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liveOutsideTrace[node].insert(instr);
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}
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}
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}
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}
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}
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}
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//Create nodes and edges for this BB
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buildNodesAndEdges(ignoreInstrs, DA, machineTollvm, liveOutsideTrace);
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}
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//Copies the graph and keeps a map from old to new nodes
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MSchedGraphSB::MSchedGraphSB(const MSchedGraphSB &G,
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std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes)
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: Target(G.Target) {
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BBs = G.BBs;
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std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> oldToNew;
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//Copy all nodes
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for(MSchedGraphSB::const_iterator N = G.GraphMap.begin(),
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NE = G.GraphMap.end(); N != NE; ++N) {
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MSchedGraphSBNode *newNode = new MSchedGraphSBNode(*(N->second));
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oldToNew[&*(N->second)] = newNode;
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newNodes[newNode] = &*(N->second);
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GraphMap[&*(N->first)] = newNode;
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}
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//Loop over nodes and update edges to point to new nodes
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for(MSchedGraphSB::iterator N = GraphMap.begin(), NE = GraphMap.end();
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N != NE; ++N) {
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//Get the node we are dealing with
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MSchedGraphSBNode *node = &*(N->second);
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node->setParent(this);
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//Loop over nodes successors and predecessors and update to the new nodes
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for(unsigned i = 0; i < node->pred_size(); ++i) {
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node->setPredecessor(i, oldToNew[node->getPredecessor(i)]);
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}
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for(unsigned i = 0; i < node->succ_size(); ++i) {
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MSchedGraphSBEdge *edge = node->getSuccessor(i);
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MSchedGraphSBNode *oldDest = edge->getDest();
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edge->setDest(oldToNew[oldDest]);
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}
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}
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}
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//Deconstructor, deletes all nodes in the graph
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MSchedGraphSB::~MSchedGraphSB () {
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for(MSchedGraphSB::iterator I = GraphMap.begin(), E = GraphMap.end();
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I != E; ++I)
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delete I->second;
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}
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//Print out graph
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void MSchedGraphSB::print(std::ostream &os) const {
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for(MSchedGraphSB::const_iterator N = GraphMap.begin(), NE = GraphMap.end();
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N != NE; ++N) {
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//Get the node we are dealing with
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MSchedGraphSBNode *node = &*(N->second);
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os << "Node Start\n";
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node->print(os);
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os << "Successors:\n";
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//print successors
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for(unsigned i = 0; i < node->succ_size(); ++i) {
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MSchedGraphSBEdge *edge = node->getSuccessor(i);
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MSchedGraphSBNode *oldDest = edge->getDest();
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oldDest->print(os);
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}
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os << "Node End\n";
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}
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}
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//Calculate total delay
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int MSchedGraphSB::totalDelay() {
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int sum = 0;
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for(MSchedGraphSB::const_iterator N = GraphMap.begin(), NE = GraphMap.end();
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N != NE; ++N) {
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//Get the node we are dealing with
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MSchedGraphSBNode *node = &*(N->second);
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sum += node->getLatency();
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}
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return sum;
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}
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bool MSchedGraphSB::instrCauseException(MachineOpCode opCode) {
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//Check for integer divide
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if(opCode == V9::SDIVXr || opCode == V9::SDIVXi
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|| opCode == V9::UDIVXr || opCode == V9::UDIVXi)
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return true;
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//Check for loads or stores
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const TargetInstrInfo *MTI = Target.getInstrInfo();
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//if( MTI->isLoad(opCode) ||
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if(MTI->isStore(opCode))
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return true;
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//Check for any floating point operation
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const TargetSchedInfo *msi = Target.getSchedInfo();
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InstrSchedClass sc = msi->getSchedClass(opCode);
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//FIXME: Should check for floating point instructions!
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//if(sc == SPARC_FGA || sc == SPARC_FGM)
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//return true;
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return false;
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}
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//Add edges between the nodes
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void MSchedGraphSB::buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs,
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DependenceAnalyzer &DA,
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std::map<MachineInstr*, Instruction*> &machineTollvm,
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std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > &liveOutsideTrace) {
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//Get Machine target information for calculating latency
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const TargetInstrInfo *MTI = Target.getInstrInfo();
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std::vector<MSchedGraphSBNode*> memInstructions;
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std::map<int, std::vector<OpIndexNodePair> > regNumtoNodeMap;
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std::map<const Value*, std::vector<OpIndexNodePair> > valuetoNodeMap;
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//Save PHI instructions to deal with later
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std::vector<const MachineInstr*> phiInstrs;
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unsigned index = 0;
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MSchedGraphSBNode *lastPred = 0;
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for(std::vector<const MachineBasicBlock*>::iterator B = BBs.begin(),
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BE = BBs.end(); B != BE; ++B) {
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const MachineBasicBlock *BB = *B;
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//Loop over instructions in MBB and add nodes and edges
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for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end();
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MI != e; ++MI) {
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//Ignore indvar instructions
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if(ignoreInstrs.count(MI)) {
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++index;
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continue;
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}
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//Get each instruction of machine basic block, get the delay
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//using the op code, create a new node for it, and add to the
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//graph.
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MachineOpCode opCode = MI->getOpcode();
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int delay;
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//Get delay
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delay = MTI->maxLatency(opCode);
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//Create new node for this machine instruction and add to the graph.
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//Create only if not a nop
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if(MTI->isNop(opCode))
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continue;
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//Sparc BE does not use PHI opcode, so assert on this case
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assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
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bool isBranch = false;
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//Skip branches
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if(MTI->isBranch(opCode))
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continue;
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//Node is created and added to the graph automatically
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MSchedGraphSBNode *node = 0;
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if(!GraphMap.count(MI)){
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node = new MSchedGraphSBNode(MI, this, index, delay);
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DEBUG(std::cerr << "Created Node: " << *node << "\n");
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}
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else {
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node = GraphMap[MI];
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if(node->isPredicate()) {
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//Create edge between this node and last pred, then switch to new pred
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if(lastPred) {
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lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
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MSchedGraphSBEdge::NonDataDep, 0);
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if(liveOutsideTrace.count(lastPred)) {
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for(std::set<MachineInstr*>::iterator L = liveOutsideTrace[lastPred].begin(), LE = liveOutsideTrace[lastPred].end(); L != LE; ++L)
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lastPred->addOutEdge(GraphMap[*L], MSchedGraphSBEdge::PredDep,
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MSchedGraphSBEdge::NonDataDep, 1);
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}
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}
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lastPred = node;
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}
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}
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//Add dependencies to instructions that cause exceptions
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if(lastPred)
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lastPred->print(std::cerr);
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if(!node->isPredicate() && instrCauseException(opCode)) {
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if(lastPred) {
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lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
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MSchedGraphSBEdge::NonDataDep, 0);
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}
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}
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//Check OpCode to keep track of memory operations to add memory
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//dependencies later.
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if(MTI->isLoad(opCode) || MTI->isStore(opCode))
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memInstructions.push_back(node);
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//Loop over all operands, and put them into the register number to
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//graph node map for determining dependencies
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//If an operands is a use/def, we have an anti dependence to itself
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for(unsigned i=0; i < MI->getNumOperands(); ++i) {
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//Get Operand
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const MachineOperand &mOp = MI->getOperand(i);
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//Check if it has an allocated register
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if(mOp.hasAllocatedReg()) {
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int regNum = mOp.getReg();
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if(regNum != SparcV9::g0) {
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//Put into our map
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regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
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}
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continue;
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|
}
|
|
|
|
|
|
//Add virtual registers dependencies
|
|
//Check if any exist in the value map already and create dependencies
|
|
//between them.
|
|
if(mOp.getType() == MachineOperand::MO_VirtualRegister
|
|
|| mOp.getType() == MachineOperand::MO_CCRegister) {
|
|
|
|
//Make sure virtual register value is not null
|
|
assert((mOp.getVRegValue() != NULL) && "Null value is defined");
|
|
|
|
//Check if this is a read operation in a phi node, if so DO NOT PROCESS
|
|
if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
|
|
DEBUG(std::cerr << "Read Operation in a PHI node\n");
|
|
continue;
|
|
}
|
|
|
|
if (const Value* srcI = mOp.getVRegValue()) {
|
|
|
|
//Find value in the map
|
|
std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
|
|
= valuetoNodeMap.find(srcI);
|
|
|
|
//If there is something in the map already, add edges from
|
|
//those instructions
|
|
//to this one we are processing
|
|
if(V != valuetoNodeMap.end()) {
|
|
addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
|
|
|
|
//Add to value map
|
|
V->second.push_back(std::make_pair(i,node));
|
|
}
|
|
//Otherwise put it in the map
|
|
else
|
|
//Put into value map
|
|
valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
|
|
}
|
|
}
|
|
}
|
|
++index;
|
|
}
|
|
|
|
//Loop over LLVM BB, examine phi instructions, and add them to our
|
|
//phiInstr list to process
|
|
const BasicBlock *llvm_bb = BB->getBasicBlock();
|
|
for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end();
|
|
I != E; ++I) {
|
|
if(const PHINode *PN = dyn_cast<PHINode>(I)) {
|
|
MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
|
|
for (unsigned j = 0; j < tempMvec.size(); j++) {
|
|
if(!ignoreInstrs.count(tempMvec[j])) {
|
|
DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
|
|
phiInstrs.push_back((MachineInstr*) tempMvec[j]);
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
addMemEdges(memInstructions, DA, machineTollvm);
|
|
addMachRegEdges(regNumtoNodeMap);
|
|
|
|
//Finally deal with PHI Nodes and Value*
|
|
for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(),
|
|
E = phiInstrs.end(); I != E; ++I) {
|
|
|
|
//Get Node for this instruction
|
|
std::map<const MachineInstr*, MSchedGraphSBNode*>::iterator X;
|
|
X = find(*I);
|
|
|
|
if(X == GraphMap.end())
|
|
continue;
|
|
|
|
MSchedGraphSBNode *node = X->second;
|
|
|
|
DEBUG(std::cerr << "Adding ite diff edges for node: " << *node << "\n");
|
|
|
|
//Loop over operands for this instruction and add value edges
|
|
for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
|
|
//Get Operand
|
|
const MachineOperand &mOp = (*I)->getOperand(i);
|
|
if((mOp.getType() == MachineOperand::MO_VirtualRegister
|
|
|| mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
|
|
|
|
//find the value in the map
|
|
if (const Value* srcI = mOp.getVRegValue()) {
|
|
|
|
//Find value in the map
|
|
std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
|
|
= valuetoNodeMap.find(srcI);
|
|
|
|
//If there is something in the map already, add edges from
|
|
//those instructions
|
|
//to this one we are processing
|
|
if(V != valuetoNodeMap.end()) {
|
|
addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
|
|
phiInstrs, 1);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
//Add dependencies for Value*s
|
|
void MSchedGraphSB::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
|
|
MSchedGraphSBNode *destNode, bool nodeIsUse,
|
|
bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
|
|
|
|
for(std::vector<OpIndexNodePair>::iterator I = NodesInMap.begin(),
|
|
E = NodesInMap.end(); I != E; ++I) {
|
|
|
|
//Get node in vectors machine operand that is the same value as node
|
|
MSchedGraphSBNode *srcNode = I->second;
|
|
MachineOperand mOp = srcNode->getInst()->getOperand(I->first);
|
|
|
|
if(diff > 0)
|
|
if(std::find(phiInstrs.begin(), phiInstrs.end(), srcNode->getInst()) == phiInstrs.end())
|
|
continue;
|
|
|
|
//Node is a Def, so add output dep.
|
|
if(nodeIsDef) {
|
|
if(mOp.isUse()) {
|
|
DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
|
|
srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
|
|
MSchedGraphSBEdge::AntiDep, diff);
|
|
}
|
|
if(mOp.isDef()) {
|
|
DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
|
|
srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
|
|
MSchedGraphSBEdge::OutputDep, diff);
|
|
}
|
|
}
|
|
if(nodeIsUse) {
|
|
if(mOp.isDef()) {
|
|
DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
|
|
srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
|
|
MSchedGraphSBEdge::TrueDep, diff);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//Add dependencies for machine registers across iterations
|
|
void MSchedGraphSB::addMachRegEdges(std::map<int, std::vector<OpIndexNodePair> >& regNumtoNodeMap) {
|
|
//Loop over all machine registers in the map, and add dependencies
|
|
//between the instructions that use it
|
|
typedef std::map<int, std::vector<OpIndexNodePair> > regNodeMap;
|
|
for(regNodeMap::iterator I = regNumtoNodeMap.begin();
|
|
I != regNumtoNodeMap.end(); ++I) {
|
|
//Get the register number
|
|
int regNum = (*I).first;
|
|
|
|
//Get Vector of nodes that use this register
|
|
std::vector<OpIndexNodePair> Nodes = (*I).second;
|
|
|
|
//Loop over nodes and determine the dependence between the other
|
|
//nodes in the vector
|
|
for(unsigned i =0; i < Nodes.size(); ++i) {
|
|
|
|
//Get src node operator index that uses this machine register
|
|
int srcOpIndex = Nodes[i].first;
|
|
|
|
//Get the actual src Node
|
|
MSchedGraphSBNode *srcNode = Nodes[i].second;
|
|
|
|
//Get Operand
|
|
const MachineOperand &srcMOp = srcNode->getInst()->getOperand(srcOpIndex);
|
|
|
|
bool srcIsUseandDef = srcMOp.isDef() && srcMOp.isUse();
|
|
bool srcIsUse = srcMOp.isUse() && !srcMOp.isDef();
|
|
|
|
|
|
//Look at all instructions after this in execution order
|
|
for(unsigned j=i+1; j < Nodes.size(); ++j) {
|
|
|
|
//Sink node is a write
|
|
if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
|
|
//Src only uses the register (read)
|
|
if(srcIsUse)
|
|
srcNode->addOutEdge(Nodes[j].second,
|
|
MSchedGraphSBEdge::MachineRegister,
|
|
MSchedGraphSBEdge::AntiDep);
|
|
|
|
else if(srcIsUseandDef) {
|
|
srcNode->addOutEdge(Nodes[j].second,
|
|
MSchedGraphSBEdge::MachineRegister,
|
|
MSchedGraphSBEdge::AntiDep);
|
|
|
|
srcNode->addOutEdge(Nodes[j].second,
|
|
MSchedGraphSBEdge::MachineRegister,
|
|
MSchedGraphSBEdge::OutputDep);
|
|
}
|
|
else
|
|
srcNode->addOutEdge(Nodes[j].second,
|
|
MSchedGraphSBEdge::MachineRegister,
|
|
MSchedGraphSBEdge::OutputDep);
|
|
}
|
|
//Dest node is a read
|
|
else {
|
|
if(!srcIsUse || srcIsUseandDef)
|
|
srcNode->addOutEdge(Nodes[j].second,
|
|
MSchedGraphSBEdge::MachineRegister,
|
|
MSchedGraphSBEdge::TrueDep);
|
|
}
|
|
|
|
}
|
|
|
|
//Look at all the instructions before this one since machine registers
|
|
//could live across iterations.
|
|
for(unsigned j = 0; j < i; ++j) {
|
|
//Sink node is a write
|
|
if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
|
|
//Src only uses the register (read)
|
|
if(srcIsUse)
|
|
srcNode->addOutEdge(Nodes[j].second,
|
|
MSchedGraphSBEdge::MachineRegister,
|
|
MSchedGraphSBEdge::AntiDep, 1);
|
|
else if(srcIsUseandDef) {
|
|
srcNode->addOutEdge(Nodes[j].second,
|
|
MSchedGraphSBEdge::MachineRegister,
|
|
MSchedGraphSBEdge::AntiDep, 1);
|
|
|
|
srcNode->addOutEdge(Nodes[j].second,
|
|
MSchedGraphSBEdge::MachineRegister,
|
|
MSchedGraphSBEdge::OutputDep, 1);
|
|
}
|
|
else
|
|
srcNode->addOutEdge(Nodes[j].second,
|
|
MSchedGraphSBEdge::MachineRegister,
|
|
MSchedGraphSBEdge::OutputDep, 1);
|
|
}
|
|
//Dest node is a read
|
|
else {
|
|
if(!srcIsUse || srcIsUseandDef)
|
|
srcNode->addOutEdge(Nodes[j].second,
|
|
MSchedGraphSBEdge::MachineRegister,
|
|
MSchedGraphSBEdge::TrueDep,1 );
|
|
}
|
|
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
//Add edges between all loads and stores
|
|
//Can be less strict with alias analysis and data dependence analysis.
|
|
void MSchedGraphSB::addMemEdges(const std::vector<MSchedGraphSBNode*>& memInst,
|
|
DependenceAnalyzer &DA,
|
|
std::map<MachineInstr*, Instruction*> &machineTollvm) {
|
|
|
|
//Get Target machine instruction info
|
|
const TargetInstrInfo *TMI = Target.getInstrInfo();
|
|
|
|
//Loop over all memory instructions in the vector
|
|
//Knowing that they are in execution, add true, anti, and output dependencies
|
|
for (unsigned srcIndex = 0; srcIndex < memInst.size(); ++srcIndex) {
|
|
|
|
MachineInstr *srcInst = (MachineInstr*) memInst[srcIndex]->getInst();
|
|
|
|
//Get the machine opCode to determine type of memory instruction
|
|
MachineOpCode srcNodeOpCode = srcInst->getOpcode();
|
|
|
|
//All instructions after this one in execution order have an
|
|
//iteration delay of 0
|
|
for(unsigned destIndex = 0; destIndex < memInst.size(); ++destIndex) {
|
|
|
|
//No self loops
|
|
if(destIndex == srcIndex)
|
|
continue;
|
|
|
|
MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
|
|
|
|
DEBUG(std::cerr << "MInst1: " << *srcInst << "\n");
|
|
DEBUG(std::cerr << "MInst2: " << *destInst << "\n");
|
|
|
|
//Assuming instructions without corresponding llvm instructions
|
|
//are from constant pools.
|
|
if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst))
|
|
continue;
|
|
|
|
bool useDepAnalyzer = true;
|
|
|
|
//Some machine loads and stores are generated by casts, so be
|
|
//conservative and always add deps
|
|
Instruction *srcLLVM = machineTollvm[srcInst];
|
|
Instruction *destLLVM = machineTollvm[destInst];
|
|
if(!isa<LoadInst>(srcLLVM)
|
|
&& !isa<StoreInst>(srcLLVM)) {
|
|
if(isa<BinaryOperator>(srcLLVM)) {
|
|
if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
|
|
continue;
|
|
}
|
|
useDepAnalyzer = false;
|
|
}
|
|
if(!isa<LoadInst>(destLLVM)
|
|
&& !isa<StoreInst>(destLLVM)) {
|
|
if(isa<BinaryOperator>(destLLVM)) {
|
|
if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
|
|
continue;
|
|
}
|
|
useDepAnalyzer = false;
|
|
}
|
|
|
|
//Use dep analysis when we have corresponding llvm loads/stores
|
|
if(useDepAnalyzer) {
|
|
bool srcBeforeDest = true;
|
|
if(destIndex < srcIndex)
|
|
srcBeforeDest = false;
|
|
|
|
DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst],
|
|
machineTollvm[destInst],
|
|
srcBeforeDest);
|
|
|
|
for(std::vector<Dependence>::iterator d = dr.dependences.begin(),
|
|
de = dr.dependences.end(); d != de; ++d) {
|
|
//Add edge from load to store
|
|
memInst[srcIndex]->addOutEdge(memInst[destIndex],
|
|
MSchedGraphSBEdge::MemoryDep,
|
|
d->getDepType(), d->getIteDiff());
|
|
|
|
}
|
|
}
|
|
//Otherwise, we can not do any further analysis and must make a dependence
|
|
else {
|
|
|
|
//Get the machine opCode to determine type of memory instruction
|
|
MachineOpCode destNodeOpCode = destInst->getOpcode();
|
|
|
|
//Get the Value* that we are reading from the load, always the first op
|
|
const MachineOperand &mOp = srcInst->getOperand(0);
|
|
const MachineOperand &mOp2 = destInst->getOperand(0);
|
|
|
|
if(mOp.hasAllocatedReg())
|
|
if(mOp.getReg() == SparcV9::g0)
|
|
continue;
|
|
if(mOp2.hasAllocatedReg())
|
|
if(mOp2.getReg() == SparcV9::g0)
|
|
continue;
|
|
|
|
DEBUG(std::cerr << "Adding dependence for machine instructions\n");
|
|
//Load-Store deps
|
|
if(TMI->isLoad(srcNodeOpCode)) {
|
|
|
|
if(TMI->isStore(destNodeOpCode))
|
|
memInst[srcIndex]->addOutEdge(memInst[destIndex],
|
|
MSchedGraphSBEdge::MemoryDep,
|
|
MSchedGraphSBEdge::AntiDep, 0);
|
|
}
|
|
else if(TMI->isStore(srcNodeOpCode)) {
|
|
if(TMI->isStore(destNodeOpCode))
|
|
memInst[srcIndex]->addOutEdge(memInst[destIndex],
|
|
MSchedGraphSBEdge::MemoryDep,
|
|
MSchedGraphSBEdge::OutputDep, 0);
|
|
|
|
else
|
|
memInst[srcIndex]->addOutEdge(memInst[destIndex],
|
|
MSchedGraphSBEdge::MemoryDep,
|
|
MSchedGraphSBEdge::TrueDep, 0);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|