mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59968 91177308-0d34-0410-b5e6-96231b3b80d8
148 lines
5.0 KiB
C++
148 lines
5.0 KiB
C++
//===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the ScheduleDAG class, which is a base class used by
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// scheduling implementation classes.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched-instrs"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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ScheduleDAGInstrs::ScheduleDAGInstrs(MachineBasicBlock *bb,
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const TargetMachine &tm)
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: ScheduleDAG(0, bb, tm) {}
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void ScheduleDAGInstrs::BuildSchedUnits() {
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SUnits.clear();
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SUnits.reserve(BB->size());
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std::vector<SUnit *> PendingLoads;
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SUnit *Terminator = 0;
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SUnit *Chain = 0;
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SUnit *Defs[TargetRegisterInfo::FirstVirtualRegister] = {};
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std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister] = {};
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int Cost = 1; // FIXME
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for (MachineBasicBlock::iterator MII = BB->end(), MIE = BB->begin();
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MII != MIE; --MII) {
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MachineInstr *MI = prior(MII);
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SUnit *SU = NewSUnit(MI);
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for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
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const MachineOperand &MO = MI->getOperand(j);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
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std::vector<SUnit *> &UseList = Uses[Reg];
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SUnit *&Def = Defs[Reg];
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// Optionally add output and anti dependencies.
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if (Def && Def != SU)
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Def->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false,
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/*PhyReg=*/Reg, Cost, /*isAntiDep=*/MO.isUse());
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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SUnit *&Def = Defs[*Alias];
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if (Def && Def != SU)
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Def->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false,
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/*PhyReg=*/*Alias, Cost, /*isAntiDep=*/MO.isUse());
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}
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if (MO.isDef()) {
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// Add any data dependencies.
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for (unsigned i = 0, e = UseList.size(); i != e; ++i)
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if (UseList[i] != SU)
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UseList[i]->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false,
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/*PhysReg=*/Reg, Cost);
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &UseList = Uses[*Alias];
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for (unsigned i = 0, e = UseList.size(); i != e; ++i)
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if (UseList[i] != SU)
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UseList[i]->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false,
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/*PhysReg=*/*Alias, Cost);
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}
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UseList.clear();
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Def = SU;
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} else {
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UseList.push_back(SU);
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}
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}
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bool False = false;
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bool True = true;
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if (!MI->isSafeToMove(TII, False)) {
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if (Chain)
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Chain->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
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for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
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PendingLoads[k]->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
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PendingLoads.clear();
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Chain = SU;
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} else if (!MI->isSafeToMove(TII, True)) {
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if (Chain)
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Chain->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
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PendingLoads.push_back(SU);
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}
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if (Terminator && SU->Succs.empty())
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Terminator->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false);
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if (MI->getDesc().isTerminator() || MI->isLabel())
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Terminator = SU;
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// Assign the Latency field of SU using target-provided information.
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ComputeLatency(SU);
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}
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}
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void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
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const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
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// Compute the latency for the node. We use the sum of the latencies for
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// all nodes flagged together into this SUnit.
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SU->Latency =
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InstrItins.getLatency(SU->getInstr()->getDesc().getSchedClass());
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}
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void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
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SU->getInstr()->dump();
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}
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std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
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std::string s;
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raw_string_ostream oss(s);
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SU->getInstr()->print(oss);
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return oss.str();
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}
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// EmitSchedule - Emit the machine code in scheduled order.
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MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
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// For MachineInstr-based scheduling, we're rescheduling the instructions in
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// the block, so start by removing them from the block.
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while (!BB->empty())
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BB->remove(BB->begin());
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for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
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SUnit *SU = Sequence[i];
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if (!SU) {
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// Null SUnit* is a noop.
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EmitNoop();
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continue;
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}
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BB->push_back(SU->getInstr());
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}
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return BB;
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}
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