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57fa38225c
Add a test case to show fewer instructions are needed to load an immediate with the new way of loading immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148908 91177308-0d34-0410-b5e6-96231b3b80d8
413 lines
13 KiB
C++
413 lines
13 KiB
C++
//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MIPS target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-isel"
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#include "Mips.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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namespace {
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class MipsDAGToDAGISel : public SelectionDAGISel {
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/// TM - Keep a reference to MipsTargetMachine.
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MipsTargetMachine &TM;
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const MipsSubtarget &Subtarget;
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public:
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explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
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SelectionDAGISel(tm),
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TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
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// Pass Name
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virtual const char *getPassName() const {
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return "MIPS DAG->DAG Pattern Instruction Selection";
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}
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private:
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// Include the pieces autogenerated from the target description.
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#include "MipsGenDAGISel.inc"
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/// getTargetMachine - Return a reference to the TargetMachine, casted
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/// to the target-specific type.
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const MipsTargetMachine &getTargetMachine() {
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return static_cast<const MipsTargetMachine &>(TM);
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}
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/// getInstrInfo - Return a reference to the TargetInstrInfo, casted
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/// to the target-specific type.
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const MipsInstrInfo *getInstrInfo() {
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return getTargetMachine().getInstrInfo();
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}
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SDNode *getGlobalBaseReg();
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std::pair<SDNode*, SDNode*> SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl,
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EVT Ty, bool HasLo, bool HasHi);
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SDNode *Select(SDNode *N);
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// Complex Pattern.
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bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
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// getImm - Return a target constant with the specified value.
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inline SDValue getImm(const SDNode *Node, unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
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}
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps);
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};
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// GOT address into a register.
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SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
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unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
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return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
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}
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsDAGToDAGISel::
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SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
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EVT ValTy = Addr.getValueType();
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unsigned GPReg = ValTy == MVT::i32 ? Mips::GP : Mips::GP_64;
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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Offset = CurDAG->getTargetConstant(0, ValTy);
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return true;
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}
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// on PIC code Load GA
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if (Addr.getOpcode() == MipsISD::Wrapper) {
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Base = CurDAG->getRegister(GPReg, ValTy);
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Offset = Addr.getOperand(0);
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return true;
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}
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if (TM.getRelocationModel() != Reloc::PIC_) {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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}
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// Addresses of the form FI+const or FI|const
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<16>(CN->getSExtValue())) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0)))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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else
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
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return true;
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}
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}
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD) {
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// When loading from constant pools, load the lower address part in
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// the instruction itself. Example, instead of:
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// lui $2, %hi($CPI1_0)
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// addiu $2, $2, %lo($CPI1_0)
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// lwc1 $f0, 0($2)
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// Generate:
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// lui $2, %hi($CPI1_0)
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// lwc1 $f0, %lo($CPI1_0)($2)
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if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
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SDValue LoVal = Addr.getOperand(1);
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if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
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isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
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Base = Addr.getOperand(0);
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Offset = LoVal.getOperand(0);
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return true;
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}
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}
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, ValTy);
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return true;
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}
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/// Select multiply instructions.
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std::pair<SDNode*, SDNode*>
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MipsDAGToDAGISel::SelectMULT(SDNode *N, unsigned Opc, DebugLoc dl, EVT Ty,
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bool HasLo, bool HasHi) {
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SDNode *Lo = 0, *Hi = 0;
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SDNode *Mul = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N->getOperand(0),
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N->getOperand(1));
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SDValue InFlag = SDValue(Mul, 0);
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if (HasLo) {
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Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
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Ty, MVT::Glue, InFlag);
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InFlag = SDValue(Lo, 1);
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}
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if (HasHi)
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Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
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Ty, InFlag);
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return std::make_pair(Lo, Hi);
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}
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/// Select instructions not customized! Used for
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/// expanded, promoted and normal instructions
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SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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DebugLoc dl = Node->getDebugLoc();
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// Dump information about the Node being selected
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DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
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return NULL;
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}
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///
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// Instruction Selection not handled by the auto-generated
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// tablegen selection should be handled here.
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///
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EVT NodeTy = Node->getValueType(0);
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unsigned MultOpc;
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switch(Opcode) {
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default: break;
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case ISD::SUBE:
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case ISD::ADDE: {
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SDValue InFlag = Node->getOperand(2), CmpLHS;
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unsigned Opc = InFlag.getOpcode(); (void)Opc;
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assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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(Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
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"(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
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unsigned MOp;
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if (Opcode == ISD::ADDE) {
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CmpLHS = InFlag.getValue(0);
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MOp = Mips::ADDu;
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} else {
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CmpLHS = InFlag.getOperand(0);
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MOp = Mips::SUBu;
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}
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SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
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SDValue LHS = Node->getOperand(0);
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SDValue RHS = Node->getOperand(1);
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EVT VT = LHS.getValueType();
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SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
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SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
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SDValue(Carry,0), RHS);
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return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
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LHS, SDValue(AddCarry,0));
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}
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/// Mul with two results
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case ISD::SMUL_LOHI:
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case ISD::UMUL_LOHI: {
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if (NodeTy == MVT::i32)
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MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
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else
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MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
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std::pair<SDNode*, SDNode*> LoHi = SelectMULT(Node, MultOpc, dl, NodeTy,
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true, true);
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if (!SDValue(Node, 0).use_empty())
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ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
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if (!SDValue(Node, 1).use_empty())
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ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
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return NULL;
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}
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/// Special Muls
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case ISD::MUL: {
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// Mips32 has a 32-bit three operand mul instruction.
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if (Subtarget.hasMips32() && NodeTy == MVT::i32)
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break;
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return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
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dl, NodeTy, true, false).first;
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}
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case ISD::MULHS:
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case ISD::MULHU: {
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if (NodeTy == MVT::i32)
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MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
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else
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MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
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return SelectMULT(Node, MultOpc, dl, NodeTy, false, true).second;
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}
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// Get target GOT address.
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case ISD::GLOBAL_OFFSET_TABLE:
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return getGlobalBaseReg();
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case ISD::ConstantFP: {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
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if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
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if (Subtarget.hasMips64()) {
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SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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Mips::ZERO_64, MVT::i64);
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return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
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}
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SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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Mips::ZERO, MVT::i32);
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return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
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Zero);
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}
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break;
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}
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case ISD::Constant: {
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const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
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unsigned Size = CN->getValueSizeInBits(0);
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if (Size == 32)
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break;
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MipsAnalyzeImmediate AnalyzeImm;
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int64_t Imm = CN->getSExtValue();
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const MipsAnalyzeImmediate::InstSeq &Seq =
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AnalyzeImm.Analyze(Imm, Size, false);
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MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
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DebugLoc DL = CN->getDebugLoc();
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SDNode *RegOpnd;
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SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
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MVT::i64);
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// The first instruction can be a LUi which is different from other
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// instructions (ADDiu, ORI and SLL) in that it does not have a register
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// operand.
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if (Inst->Opc == Mips::LUi64)
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RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
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else
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RegOpnd =
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CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
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CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
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ImmOpnd);
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// The remaining instructions in the sequence are handled here.
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for (++Inst; Inst != Seq.end(); ++Inst) {
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ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
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MVT::i64);
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RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
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SDValue(RegOpnd, 0), ImmOpnd);
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}
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return RegOpnd;
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}
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case MipsISD::ThreadPointer: {
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EVT PtrVT = TLI.getPointerTy();
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unsigned RdhwrOpc, SrcReg, DestReg;
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if (PtrVT == MVT::i32) {
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RdhwrOpc = Mips::RDHWR;
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SrcReg = Mips::HWR29;
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DestReg = Mips::V1;
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} else {
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RdhwrOpc = Mips::RDHWR64;
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SrcReg = Mips::HWR29_64;
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DestReg = Mips::V1_64;
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}
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SDNode *Rdhwr =
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CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
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Node->getValueType(0),
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CurDAG->getRegister(SrcReg, PtrVT));
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SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
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SDValue(Rdhwr, 0));
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SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, PtrVT);
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ReplaceUses(SDValue(Node, 0), ResNode);
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return ResNode.getNode();
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}
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}
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// Select the default instruction
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SDNode *ResNode = SelectCode(Node);
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DEBUG(errs() << "=> ");
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if (ResNode == NULL || ResNode == Node)
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DEBUG(Node->dump(CurDAG));
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else
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DEBUG(ResNode->dump(CurDAG));
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DEBUG(errs() << "\n");
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return ResNode;
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}
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bool MipsDAGToDAGISel::
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SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
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OutOps.push_back(Op);
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return false;
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}
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/// createMipsISelDag - This pass converts a legalized DAG into a
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/// MIPS-specific DAG, ready for instruction scheduling.
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FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
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return new MipsDAGToDAGISel(TM);
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}
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