llvm-6502/test/MC/X86
Chad Rosier dd2e895022 [ms-inline asm] Extend support for parsing Intel bracketed memory operands that
have an arbitrary ordering of the base register, index register and displacement.
rdar://12527141


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14 22:31:35 +00:00
..
AlignedBundling
3DNow.s
2011-09-06-NoNewline.s
address-size.s
intel-syntax-2.s
intel-syntax-encoding.s
intel-syntax.s
lit.local.cfg
padlock.s
x86_64-avx-clmul-encoding.s
x86_64-avx-encoding.s
x86_64-bmi-encoding.s
x86_64-encoding.s
x86_64-fma3-encoding.s
x86_64-fma4-encoding.s
x86_64-imm-widths.s
x86_64-rtm-encoding.s
x86_64-sse4a.s
x86_64-xop-encoding.s
x86_directives.s
x86_errors.s
x86_nop.s
x86_operands.s
x86-32-avx.s
x86-32-coverage.s
x86-32-fma3.s
x86-32-ms-inline-asm.s
x86-32.s
x86-64.s