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operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203865 91177308-0d34-0410-b5e6-96231b3b80d8
264 lines
9.5 KiB
C++
264 lines
9.5 KiB
C++
//===-- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Copies from VGPR to SGPR registers are illegal and the register coalescer
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/// will sometimes generate these illegal copies in situations like this:
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///
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/// Register Class <vsrc> is the union of <vgpr> and <sgpr>
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///
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/// BB0:
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/// %vreg0 <sgpr> = SCALAR_INST
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/// %vreg1 <vsrc> = COPY %vreg0 <sgpr>
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/// ...
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/// BRANCH %cond BB1, BB2
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/// BB1:
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/// %vreg2 <vgpr> = VECTOR_INST
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/// %vreg3 <vsrc> = COPY %vreg2 <vgpr>
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/// BB2:
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/// %vreg4 <vsrc> = PHI %vreg1 <vsrc>, <BB#0>, %vreg3 <vrsc>, <BB#1>
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/// %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc>
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///
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///
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/// The coalescer will begin at BB0 and eliminate its copy, then the resulting
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/// code will look like this:
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///
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/// BB0:
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/// %vreg0 <sgpr> = SCALAR_INST
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/// ...
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/// BRANCH %cond BB1, BB2
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/// BB1:
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/// %vreg2 <vgpr> = VECTOR_INST
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/// %vreg3 <vsrc> = COPY %vreg2 <vgpr>
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/// BB2:
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/// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <vsrc>, <BB#1>
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/// %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
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///
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/// Now that the result of the PHI instruction is an SGPR, the register
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/// allocator is now forced to constrain the register class of %vreg3 to
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/// <sgpr> so we end up with final code like this:
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///
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/// BB0:
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/// %vreg0 <sgpr> = SCALAR_INST
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/// ...
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/// BRANCH %cond BB1, BB2
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/// BB1:
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/// %vreg2 <vgpr> = VECTOR_INST
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/// %vreg3 <sgpr> = COPY %vreg2 <vgpr>
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/// BB2:
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/// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <sgpr>, <BB#1>
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/// %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
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///
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/// Now this code contains an illegal copy from a VGPR to an SGPR.
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///
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/// In order to avoid this problem, this pass searches for PHI instructions
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/// which define a <vsrc> register and constrains its definition class to
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/// <vgpr> if the user of the PHI's definition register is a vector instruction.
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/// If the PHI's definition class is constrained to <vgpr> then the coalescer
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/// will be unable to perform the COPY removal from the above example which
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/// ultimately led to the creation of an illegal COPY.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sgpr-copies"
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#include "AMDGPU.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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namespace {
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class SIFixSGPRCopies : public MachineFunctionPass {
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private:
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static char ID;
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const TargetRegisterClass *inferRegClassFromUses(const SIRegisterInfo *TRI,
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const MachineRegisterInfo &MRI,
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unsigned Reg,
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unsigned SubReg) const;
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const TargetRegisterClass *inferRegClassFromDef(const SIRegisterInfo *TRI,
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const MachineRegisterInfo &MRI,
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unsigned Reg,
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unsigned SubReg) const;
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bool isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI,
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const MachineRegisterInfo &MRI) const;
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public:
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SIFixSGPRCopies(TargetMachine &tm) : MachineFunctionPass(ID) { }
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const {
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return "SI Fix SGPR copies";
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}
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};
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} // End anonymous namespace
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char SIFixSGPRCopies::ID = 0;
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FunctionPass *llvm::createSIFixSGPRCopiesPass(TargetMachine &tm) {
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return new SIFixSGPRCopies(tm);
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}
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static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) {
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const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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if (!MI.getOperand(i).isReg() ||
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!TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg()))
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continue;
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if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
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return true;
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}
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return false;
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}
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/// This functions walks the use list of Reg until it finds an Instruction
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/// that isn't a COPY returns the register class of that instruction.
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/// \return The register defined by the first non-COPY instruction.
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const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromUses(
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const SIRegisterInfo *TRI,
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const MachineRegisterInfo &MRI,
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unsigned Reg,
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unsigned SubReg) const {
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// The Reg parameter to the function must always be defined by either a PHI
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// or a COPY, therefore it cannot be a physical register.
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assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
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"Reg cannot be a physical register");
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const TargetRegisterClass *RC = MRI.getRegClass(Reg);
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RC = TRI->getSubRegClass(RC, SubReg);
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for (MachineRegisterInfo::use_instr_iterator
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I = MRI.use_instr_begin(Reg), E = MRI.use_instr_end(); I != E; ++I) {
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switch (I->getOpcode()) {
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case AMDGPU::COPY:
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RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI,
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I->getOperand(0).getReg(),
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I->getOperand(0).getSubReg()));
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break;
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}
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}
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return RC;
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}
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const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromDef(
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const SIRegisterInfo *TRI,
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const MachineRegisterInfo &MRI,
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unsigned Reg,
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unsigned SubReg) const {
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if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
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const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg);
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return TRI->getSubRegClass(RC, SubReg);
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}
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MachineInstr *Def = MRI.getVRegDef(Reg);
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if (Def->getOpcode() != AMDGPU::COPY) {
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return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg);
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}
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return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(),
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Def->getOperand(1).getSubReg());
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}
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bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy,
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const SIRegisterInfo *TRI,
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const MachineRegisterInfo &MRI) const {
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unsigned DstReg = Copy.getOperand(0).getReg();
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unsigned SrcReg = Copy.getOperand(1).getReg();
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unsigned SrcSubReg = Copy.getOperand(1).getSubReg();
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const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
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const TargetRegisterClass *SrcRC;
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if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
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DstRC == &AMDGPU::M0RegRegClass)
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return false;
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SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg);
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return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC);
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}
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bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
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MF.getTarget().getRegisterInfo());
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const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
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MF.getTarget().getInstrInfo());
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI) {
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MachineBasicBlock &MBB = *BI;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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if (MI.getOpcode() == AMDGPU::COPY && isVGPRToSGPRCopy(MI, TRI, MRI)) {
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DEBUG(dbgs() << "Fixing VGPR -> SGPR copy:\n");
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DEBUG(MI.print(dbgs()));
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TII->moveToVALU(MI);
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}
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switch (MI.getOpcode()) {
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default: continue;
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case AMDGPU::PHI: {
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DEBUG(dbgs() << " Fixing PHI:\n");
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DEBUG(MI.print(dbgs()));
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for (unsigned i = 1; i < MI.getNumOperands(); i+=2) {
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unsigned Reg = MI.getOperand(i).getReg();
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const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg,
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MI.getOperand(0).getSubReg());
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MRI.constrainRegClass(Reg, RC);
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}
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unsigned Reg = MI.getOperand(0).getReg();
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const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg,
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MI.getOperand(0).getSubReg());
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if (TRI->getCommonSubClass(RC, &AMDGPU::VReg_32RegClass)) {
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MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass);
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}
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if (!TRI->isSGPRClass(MRI.getRegClass(Reg)))
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break;
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// If a PHI node defines an SGPR and any of its operands are VGPRs,
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// then we need to move it to the VALU.
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for (unsigned i = 1; i < MI.getNumOperands(); i+=2) {
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unsigned Reg = MI.getOperand(i).getReg();
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if (TRI->hasVGPRs(MRI.getRegClass(Reg))) {
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TII->moveToVALU(MI);
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break;
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}
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}
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break;
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}
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case AMDGPU::REG_SEQUENCE: {
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if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) ||
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!hasVGPROperands(MI, TRI))
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continue;
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DEBUG(dbgs() << "Fixing REG_SEQUENCE:\n");
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DEBUG(MI.print(dbgs()));
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TII->moveToVALU(MI);
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break;
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}
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}
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}
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}
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return false;
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}
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