Jack Carter d3107fbc54 Fix the invalid opcode for Mips branch instructions in the assembler ... For mips a branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Previously, the code generator did not perform the shift of the immediate branch offset which resulted in wrong instruction opcode. This patch fixes the issue. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-22 00:29:10 +00:00
..
AArch64
ARM	Fix pr13145 - Naming a function like a register name confuses the asm parser.	2013-03-19 23:44:03 +00:00
AsmParser	AsmParser: More generic support for integer type suffices.	2013-02-26 20:17:10 +00:00
COFF
Disassembler	Fixes disassembler crashes on 2013 Haswell RTM instructions.	2013-03-11 21:17:13 +00:00
ELF	Fix the FDE encoding to be relative on ELF.	2013-03-15 05:51:57 +00:00
MachO
Markup
MBlaze
Mips	Fix the invalid opcode for Mips branch instructions in the assembler	2013-03-22 00:29:10 +00:00
PowerPC
X86	Post process ADC/SBB and use a shorter encoding if they use a sign extended immediate.	2013-03-18 03:34:55 +00:00