mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-26 06:29:20 +00:00
bbe51362d5
Added fp register clobbering during calls. Added AsmPrinter support for "fmask", a bitmask that indicates where on the stack the fp callee saved registers are. Fixed the stack frame layout for Mips, now the callee saved regs are in the right stack location (a little documentation about how this stack frame must look like is present in MipsRegisterInfo.cpp). This was done using the method MipsRegisterInfo::adjustMipsStackFrame To be more clear, these are examples of what is solves : 1) FP and RA are also callee saved, and despite they aren't in CSI they must be saved before the fp callee saved registers. 2) The ABI requires that local varibles are allocated before the callee saved register area, the opposite behavior from the default allocation. 3) CPU and FPU saved register area must be aligned independent of each other. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54403 91177308-0d34-0410-b5e6-96231b3b80d8
126 lines
3.9 KiB
C++
126 lines
3.9 KiB
C++
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Mips target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsTargetAsmInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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using namespace llvm;
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// Register the target.
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static RegisterTarget<MipsTargetMachine> X("mips", " Mips");
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static RegisterTarget<MipselTargetMachine> Y("mipsel", " Mipsel");
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const TargetAsmInfo *MipsTargetMachine::
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createTargetAsmInfo() const
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{
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return new MipsTargetAsmInfo(*this);
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}
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// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
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// The stack is always 8 byte aligned
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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// offset from the stack/frame pointer, using StackGrowsUp enables
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// an easier handling.
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// Using CodeModel::Large enables different CALL behavior.
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MipsTargetMachine::
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MipsTargetMachine(const Module &M, const std::string &FS, bool isLittle=false):
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Subtarget(*this, M, FS, isLittle),
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DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32") :
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std::string("E-p:32:32:32-i8:8:32-i16:16:32")),
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InstrInfo(*this),
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FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0),
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TLInfo(*this)
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{
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// Abicall enables PIC by default
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if (Subtarget.hasABICall() && (getRelocationModel() != Reloc::Static))
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setRelocationModel(Reloc::PIC_);
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// TODO: create an option to enable long calls, like -mlong-calls,
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// that would be our CodeModel::Large. It must not work with Abicall.
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if (getCodeModel() == CodeModel::Default)
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setCodeModel(CodeModel::Small);
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}
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MipselTargetMachine::
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MipselTargetMachine(const Module &M, const std::string &FS) :
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MipsTargetMachine(M, FS, true) {}
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// return 0 and must specify -march to gen MIPS code.
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unsigned MipsTargetMachine::
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getModuleMatchQuality(const Module &M)
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{
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// We strongly match "mips*-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 5 && std::string(TT.begin(), TT.begin()+5) == "mips-")
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return 20;
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if (TT.size() >= 13 && std::string(TT.begin(),
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TT.begin()+13) == "mipsallegrex-")
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return 20;
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return 0;
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}
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// return 0 and must specify -march to gen MIPSEL code.
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unsigned MipselTargetMachine::
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getModuleMatchQuality(const Module &M)
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{
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// We strongly match "mips*el-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 7 && std::string(TT.begin(), TT.begin()+7) == "mipsel-")
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return 20;
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if (TT.size() >= 15 && std::string(TT.begin(),
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TT.begin()+15) == "mipsallegrexel-")
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return 20;
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if (TT.size() == 3 && std::string(TT.begin(), TT.begin()+3) == "psp")
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return 20;
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return 0;
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}
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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bool MipsTargetMachine::
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addInstSelector(PassManagerBase &PM, bool Fast)
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{
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PM.add(createMipsISelDag(*this));
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return false;
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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// print out the code after the passes.
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bool MipsTargetMachine::
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addPreEmitPass(PassManagerBase &PM, bool Fast)
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{
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PM.add(createMipsDelaySlotFillerPass(*this));
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return true;
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}
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// Implements the AssemblyEmitter for the target. Must return
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// true if AssemblyEmitter is supported
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bool MipsTargetMachine::
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addAssemblyEmitter(PassManagerBase &PM, bool Fast,
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std::ostream &Out)
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{
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// Output assembly language.
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PM.add(createMipsCodePrinterPass(Out, *this));
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return false;
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}
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