Andrew Trick 6606ef0e98 MI-Sched: Model "reserved" processor resources. ... This allows a target to use MI-Sched as an in-order scheduler that will model strict resource conflicts without defining a processor itinerary. Instead, the target can now use the new per-operand machine model and define in-order resources with BufferSize=0. For example, this would allow restricting the type of operations that can be formed into a dispatch group. (Normally NumMicroOps is sufficient to enforce dispatch groups). If the intent is to model latency in in-order pipeline, as opposed to resource conflicts, then a resource with BufferSize=1 should be defined instead. This feature is only casually tested as there are no in-tree targets using it yet. However, Hal will be experimenting with POWER7. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196517 91177308-0d34-0410-b5e6-96231b3b80d8		2013-12-05 17:56:02 +00:00
..
Analysis	Correct word hyphenations	2013-12-05 05:44:44 +00:00
AsmParser
Bitcode
CodeGen	MI-Sched: Model "reserved" processor resources.	2013-12-05 17:56:02 +00:00
DebugInfo
ExecutionEngine	Remove the isImplicitlyPrivate argument of getNameWithPrefix.	2013-12-05 05:53:12 +00:00
IR	Use isIntrinsic() instead of checking for "llvm."	2013-12-05 06:05:43 +00:00
IRReader
Linker
LTO	Remove the isImplicitlyPrivate argument of getNameWithPrefix.	2013-12-05 05:53:12 +00:00
MC	Correct word hyphenations	2013-12-05 05:44:44 +00:00
Object
Option	Avoid buffer copies when a Twine already is a StringRef.	2013-12-03 18:18:28 +00:00
Support	Correct word hyphenations	2013-12-05 05:44:44 +00:00
TableGen
Target	MI-Sched: handle latency of in-order operations with the new machine model.	2013-12-05 17:55:58 +00:00
Transforms	SLPVectorizer: An in-tree vectorized entry cannot also be a scalar external use	2013-12-05 15:14:40 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile