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https://github.com/c64scene-ar/llvm-6502.git
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b3cabb44c3
RISBG can handle some ANDs for which no AND IMMEDIATE exists. It also acts as a three-operand AND for some cases where an AND IMMEDIATE could be used instead. It might be worth adding a pass to replace RISBG with AND IMMEDIATE in cases where the register operands end up being the same and where AND IMMEDIATE is smaller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186072 91177308-0d34-0410-b5e6-96231b3b80d8
134 lines
3.8 KiB
LLVM
134 lines
3.8 KiB
LLVM
; Test 8-bit atomic ANDs.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2
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; Check AND of a variable.
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; - CHECK is for the main loop.
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; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
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; RLL is set up correctly. The negation is independent of the NILL and L
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; tested in CHECK.
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; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
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; before being used, and that the low bits are set to 1. This sequence is
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; independent of the other loop prologue instructions.
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define i8 @f1(i8 *%src, i8 %b) {
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; CHECK: f1:
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; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
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; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: nr [[ROT]], %r3
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
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; CHECK: jlh [[LABEL]]
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; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f1:
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; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2: f1:
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; CHECK-SHIFT2: sll %r3, 24
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; CHECK-SHIFT2: oilf %r3, 16777215
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: nr {{%r[0-9]+}}, %r3
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw and i8 *%src, i8 %b seq_cst
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ret i8 %res
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}
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; Check the minimum signed value. We AND the rotated word with 0x80ffffff.
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define i8 @f2(i8 *%src) {
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; CHECK: f2:
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; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
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; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: nilh [[ROT]], 33023
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
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; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
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; CHECK: jlh [[LABEL]]
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; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f2:
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; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2: f2:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw and i8 *%src, i8 -128 seq_cst
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ret i8 %res
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}
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; Check ANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfeffffff.
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define i8 @f3(i8 *%src) {
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; CHECK: f3:
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; CHECK: nilh [[ROT]], 65279
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f3:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2: f3:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw and i8 *%src, i8 -2 seq_cst
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ret i8 %res
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}
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; Check ANDs of 1. We AND the rotated word with 0x01ffffff.
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define i8 @f4(i8 *%src) {
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; CHECK: f4:
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; CHECK: nilh [[ROT]], 511
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f4:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2: f4:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw and i8 *%src, i8 1 seq_cst
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ret i8 %res
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}
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; Check the maximum signed value. We AND the rotated word with 0x7fffffff.
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define i8 @f5(i8 *%src) {
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; CHECK: f5:
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; CHECK: nilh [[ROT]], 32767
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f5:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2: f5:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw and i8 *%src, i8 127 seq_cst
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ret i8 %res
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}
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; Check ANDs of a large unsigned value. We AND the rotated word with
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; 0xfdffffff.
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define i8 @f6(i8 *%src) {
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; CHECK: f6:
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; CHECK: nilh [[ROT]], 65023
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; CHECK: br %r14
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;
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; CHECK-SHIFT1: f6:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2: f6:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw and i8 *%src, i8 253 seq_cst
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ret i8 %res
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}
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