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b3cabb44c3
RISBG can handle some ANDs for which no AND IMMEDIATE exists. It also acts as a three-operand AND for some cases where an AND IMMEDIATE could be used instead. It might be worth adding a pass to replace RISBG with AND IMMEDIATE in cases where the register operands end up being the same and where AND IMMEDIATE is smaller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186072 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
1.9 KiB
LLVM
56 lines
1.9 KiB
LLVM
; Test 16-bit atomic exchange.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT
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; Check exchange with a variable.
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; - CHECK is for the main loop.
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; - CHECK-SHIFT makes sure that the negated shift count used by the second
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; RLL is set up correctly. The negation is independent of the NILL and L
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; tested in CHECK. CHECK-SHIFT also checks that %r3 is not modified before
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; being used in the RISBG (in contrast to things like atomic addition,
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; which shift %r3 left so that %b is at the high end of the word).
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define i16 @f1(i16 *%src, i16 %b) {
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; CHECK: f1:
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; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
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; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: risbg [[ROT]], %r3, 32, 47, 16
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0([[BASE]])
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; CHECK: jlh [[LABEL]]
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; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT: f1:
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; CHECK-SHIFT-NOT: %r3
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; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT-NOT: %r3
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; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT-NOT: %r3
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; CHECK-SHIFT: rll
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; CHECK-SHIFT-NOT: %r3
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; CHECK-SHIFT: risbg {{%r[0-9]+}}, %r3, 32, 47, 16
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; CHECK-SHIFT: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT: rll
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; CHECK-SHIFT: br %r14
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%res = atomicrmw xchg i16 *%src, i16 %b seq_cst
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ret i16 %res
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}
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; Check exchange with a constant. We should force the constant into
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; a register and use the sequence above.
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define i16 @f2(i16 *%src) {
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; CHECK: f2:
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; CHECK: lhi [[VALUE:%r[0-9]+]], -25536
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; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 47, 16
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; CHECK: br %r14
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;
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; CHECK-SHIFT: f2:
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; CHECK-SHIFT: br %r14
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%res = atomicrmw xchg i16 *%src, i16 40000 seq_cst
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ret i16 %res
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}
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