mirror of
https://github.com/c64scene-ar/llvm-6502.git
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fa487e83a8
Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185529 91177308-0d34-0410-b5e6-96231b3b80d8
177 lines
5.3 KiB
LLVM
177 lines
5.3 KiB
LLVM
; Test 64-bit byteswaps from memory to registers.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i64 @llvm.bswap.i64(i64 %a)
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; Check LRVG with no displacement.
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define i64 @f1(i64 *%src) {
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; CHECK: f1:
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; CHECK: lrvg %r2, 0(%r2)
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; CHECK: br %r14
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%a = load i64 *%src
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%swapped = call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %swapped
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}
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; Check the high end of the aligned LRVG range.
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define i64 @f2(i64 *%src) {
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; CHECK: f2:
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; CHECK: lrvg %r2, 524280(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65535
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%a = load i64 *%ptr
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%swapped = call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %swapped
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f3(i64 *%src) {
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; CHECK: f3:
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; CHECK: agfi %r2, 524288
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; CHECK: lrvg %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 65536
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%a = load i64 *%ptr
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%swapped = call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %swapped
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}
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; Check the high end of the negative aligned LRVG range.
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define i64 @f4(i64 *%src) {
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; CHECK: f4:
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; CHECK: lrvg %r2, -8(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -1
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%a = load i64 *%ptr
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%swapped = call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %swapped
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}
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; Check the low end of the LRVG range.
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define i64 @f5(i64 *%src) {
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; CHECK: f5:
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; CHECK: lrvg %r2, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65536
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%a = load i64 *%ptr
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%swapped = call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %swapped
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f6(i64 *%src) {
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; CHECK: f6:
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; CHECK: agfi %r2, -524296
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; CHECK: lrvg %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64 *%src, i64 -65537
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%a = load i64 *%ptr
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%swapped = call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %swapped
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}
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; Check that LRVG allows an index.
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define i64 @f7(i64 %src, i64 %index) {
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; CHECK: f7:
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; CHECK: lrvg %r2, 524287({{%r3,%r2|%r2,%r3}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i64 *
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%a = load i64 *%ptr
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%swapped = call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %swapped
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}
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; Check that volatile accesses do not use LRVG, which might access the
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; storage multple times.
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define i64 @f8(i64 *%src) {
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; CHECK: f8:
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; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
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; CHECK: lrvgr %r2, [[REG]]
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; CHECK: br %r14
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%a = load volatile i64 *%src
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%swapped = call i64 @llvm.bswap.i64(i64 %a)
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ret i64 %swapped
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}
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; Test a case where we spill the source of at least one LRVGR. We want
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; to use LRVG if possible.
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define void @f9(i64 *%ptr) {
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; CHECK: f9:
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; CHECK: lrvg {{%r[0-9]+}}, 160(%r15)
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; CHECK: br %r14
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%val0 = load volatile i64 *%ptr
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%val1 = load volatile i64 *%ptr
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%val2 = load volatile i64 *%ptr
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%val3 = load volatile i64 *%ptr
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%val4 = load volatile i64 *%ptr
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%val5 = load volatile i64 *%ptr
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%val6 = load volatile i64 *%ptr
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%val7 = load volatile i64 *%ptr
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%val8 = load volatile i64 *%ptr
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%val9 = load volatile i64 *%ptr
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%val10 = load volatile i64 *%ptr
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%val11 = load volatile i64 *%ptr
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%val12 = load volatile i64 *%ptr
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%val13 = load volatile i64 *%ptr
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%val14 = load volatile i64 *%ptr
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%val15 = load volatile i64 *%ptr
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%swapped0 = call i64 @llvm.bswap.i64(i64 %val0)
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%swapped1 = call i64 @llvm.bswap.i64(i64 %val1)
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%swapped2 = call i64 @llvm.bswap.i64(i64 %val2)
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%swapped3 = call i64 @llvm.bswap.i64(i64 %val3)
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%swapped4 = call i64 @llvm.bswap.i64(i64 %val4)
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%swapped5 = call i64 @llvm.bswap.i64(i64 %val5)
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%swapped6 = call i64 @llvm.bswap.i64(i64 %val6)
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%swapped7 = call i64 @llvm.bswap.i64(i64 %val7)
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%swapped8 = call i64 @llvm.bswap.i64(i64 %val8)
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%swapped9 = call i64 @llvm.bswap.i64(i64 %val9)
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%swapped10 = call i64 @llvm.bswap.i64(i64 %val10)
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%swapped11 = call i64 @llvm.bswap.i64(i64 %val11)
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%swapped12 = call i64 @llvm.bswap.i64(i64 %val12)
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%swapped13 = call i64 @llvm.bswap.i64(i64 %val13)
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%swapped14 = call i64 @llvm.bswap.i64(i64 %val14)
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%swapped15 = call i64 @llvm.bswap.i64(i64 %val15)
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store volatile i64 %val0, i64 *%ptr
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store volatile i64 %val1, i64 *%ptr
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store volatile i64 %val2, i64 *%ptr
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store volatile i64 %val3, i64 *%ptr
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store volatile i64 %val4, i64 *%ptr
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store volatile i64 %val5, i64 *%ptr
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store volatile i64 %val6, i64 *%ptr
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store volatile i64 %val7, i64 *%ptr
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store volatile i64 %val8, i64 *%ptr
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store volatile i64 %val9, i64 *%ptr
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store volatile i64 %val10, i64 *%ptr
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store volatile i64 %val11, i64 *%ptr
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store volatile i64 %val12, i64 *%ptr
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store volatile i64 %val13, i64 *%ptr
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store volatile i64 %val14, i64 *%ptr
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store volatile i64 %val15, i64 *%ptr
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store volatile i64 %swapped0, i64 *%ptr
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store volatile i64 %swapped1, i64 *%ptr
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store volatile i64 %swapped2, i64 *%ptr
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store volatile i64 %swapped3, i64 *%ptr
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store volatile i64 %swapped4, i64 *%ptr
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store volatile i64 %swapped5, i64 *%ptr
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store volatile i64 %swapped6, i64 *%ptr
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store volatile i64 %swapped7, i64 *%ptr
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store volatile i64 %swapped8, i64 *%ptr
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store volatile i64 %swapped9, i64 *%ptr
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store volatile i64 %swapped10, i64 *%ptr
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store volatile i64 %swapped11, i64 *%ptr
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store volatile i64 %swapped12, i64 *%ptr
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store volatile i64 %swapped13, i64 *%ptr
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store volatile i64 %swapped14, i64 *%ptr
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store volatile i64 %swapped15, i64 *%ptr
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ret void
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}
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