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https://github.com/c64scene-ar/llvm-6502.git
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193c3acbe5
the condition codes. Where the ones that do have an 's' suffix and the ones that don't don't have the suffix. The trick is if MatchInstructionImpl() fails we try again after adding a CCOut operand with the correct value and removing the 's' if present. Four simple test cases added for now, lots more to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121401 91177308-0d34-0410-b5e6-96231b3b80d8
67 lines
2.6 KiB
ArmAsm
67 lines
2.6 KiB
ArmAsm
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
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@ CHECK: nop
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@ CHECK: encoding: [0x00,0xf0,0x20,0xe3]
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nop
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@ CHECK: nopeq
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@ CHECK: encoding: [0x00,0xf0,0x20,0x03]
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nopeq
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@ CHECK: trap
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@ CHECK: encoding: [0xfe,0xde,0xff,0xe7]
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trap
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@ CHECK: bx lr
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@ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
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bx lr
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@ CHECK: vqdmull.s32 q8, d17, d16
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@ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2]
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vqdmull.s32 q8, d17, d16
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@ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9]
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@ CHECK: ldmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe8]
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@ CHECK: ldmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe9]
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ldmia r2, {r1,r3-r6,sp}
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ldmib r2, {r1,r3-r6,sp}
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ldmda r2, {r1,r3-r6,sp}
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ldmdb r2, {r1,r3-r6,sp}
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@ CHECK: stmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8]
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@ CHECK: stmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe9]
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@ CHECK: stmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe8]
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@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9]
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stmia r2, {r1,r3-r6,sp}
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stmib r2, {r1,r3-r6,sp}
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stmda r2, {r1,r3-r6,sp}
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stmdb r2, {r1,r3-r6,sp}
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@ CHECK: ldmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe8]
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@ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9]
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@ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8]
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@ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9]
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ldmia r2!, {r1,r3-r6,sp}
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ldmib r2!, {r1,r3-r6,sp}
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ldmda r2!, {r1,r3-r6,sp}
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ldmdb r2!, {r1,r3-r6,sp}
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@ CHECK: stmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe8]
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@ CHECK: stmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe9]
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@ CHECK: stmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe8]
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@ CHECK: stmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe9]
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stmia r2!, {r1,r3-r6,sp}
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stmib r2!, {r1,r3-r6,sp}
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stmda r2!, {r1,r3-r6,sp}
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stmdb r2!, {r1,r3-r6,sp}
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@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
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and r1, r2, r3
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@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
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ands r1, r2, r3
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@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
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eor r1, r2, r3
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@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
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eors r1, r2, r3
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