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and extern_weak_odr. These are the same as the non-odr versions, except that they indicate that the global will only be overridden by an *equivalent* global. In C, a function with weak linkage can be overridden by a function which behaves completely differently. This means that IP passes have to skip weak functions, since any deductions made from the function definition might be wrong, since the definition could be replaced by something completely different at link time. This is not allowed in C++, thanks to the ODR (One-Definition-Rule): if a function is replaced by another at link-time, then the new function must be the same as the original function. If a language knows that a function or other global can only be overridden by an equivalent global, it can give it the weak_odr linkage type, and the optimizers will understand that it is alright to make deductions based on the function body. The code generators on the other hand map weak and weak_odr linkage to the same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8
580 lines
18 KiB
C++
580 lines
18 KiB
C++
//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format MIPS assembly language.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-asm-printer"
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "MipsMachineFunction.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Module.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/DwarfWriter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Mangler.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cctype>
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using namespace llvm;
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STATISTIC(EmittedInsts, "Number of machine instrs printed");
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namespace {
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class VISIBILITY_HIDDEN MipsAsmPrinter : public AsmPrinter {
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const MipsSubtarget *Subtarget;
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public:
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MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
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const TargetAsmInfo *T, bool F)
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: AsmPrinter(O, TM, T, F) {
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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}
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virtual const char *getPassName() const {
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return "Mips Assembly Printer";
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}
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode);
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void printOperand(const MachineInstr *MI, int opNum);
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void printUnsignedImm(const MachineInstr *MI, int opNum);
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void printMemOperand(const MachineInstr *MI, int opNum,
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const char *Modifier = 0);
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void printFCCOperand(const MachineInstr *MI, int opNum,
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const char *Modifier = 0);
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void printModuleLevelGV(const GlobalVariable* GVar);
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void printSavedRegsBitmask(MachineFunction &MF);
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void printHex32(unsigned int Value);
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const char *emitCurrentABIString(void);
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void emitFunctionStart(MachineFunction &MF);
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void emitFunctionEnd(MachineFunction &MF);
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void emitFrameDirective(MachineFunction &MF);
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bool printInstruction(const MachineInstr *MI); // autogenerated.
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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bool doFinalization(Module &M);
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};
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} // end of anonymous namespace
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#include "MipsGenAsmWriter.inc"
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/// createMipsCodePrinterPass - Returns a pass that prints the MIPS
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/// assembly code for a MachineFunction to the given output stream,
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/// using the given target machine description. This should work
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/// regardless of whether the function is in SSA form.
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FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
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MipsTargetMachine &tm,
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bool fast) {
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return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), fast);
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}
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//===----------------------------------------------------------------------===//
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//
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// Mips Asm Directives
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//
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// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
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// Describe the stack frame.
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//
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// -- Mask directives "(f)mask bitmask, offset"
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// Tells the assembler which registers are saved and where.
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// bitmask - contain a little endian bitset indicating which registers are
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// saved on function prologue (e.g. with a 0x80000000 mask, the
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// assembler knows the register 31 (RA) is saved at prologue.
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// offset - the position before stack pointer subtraction indicating where
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// the first saved register on prologue is located. (e.g. with a
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//
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// Consider the following function prologue:
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//
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// .frame $fp,48,$ra
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// .mask 0xc0000000,-8
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// addiu $sp, $sp, -48
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// sw $ra, 40($sp)
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// sw $fp, 36($sp)
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//
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// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
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// 30 (FP) are saved at prologue. As the save order on prologue is from
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// left to right, RA is saved first. A -8 offset means that after the
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// stack pointer subtration, the first register in the mask (RA) will be
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// saved at address 48-8=40.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mask directives
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//===----------------------------------------------------------------------===//
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// Create a bitmask with all callee saved registers for CPU or Floating Point
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// registers. For CPU registers consider RA, GP and FP for saving if necessary.
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void MipsAsmPrinter::
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printSavedRegsBitmask(MachineFunction &MF)
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{
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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// CPU and FPU Saved Registers Bitmasks
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unsigned int CPUBitmask = 0;
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unsigned int FPUBitmask = 0;
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// Set the CPU and FPU Bitmasks
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(CSI[i].getReg());
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if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
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CPUBitmask |= (1 << RegNum);
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else
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FPUBitmask |= (1 << RegNum);
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}
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// Return Address and Frame registers must also be set in CPUBitmask.
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if (RI.hasFP(MF))
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CPUBitmask |= (1 << MipsRegisterInfo::
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getRegisterNumbering(RI.getFrameRegister(MF)));
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if (MF.getFrameInfo()->hasCalls())
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CPUBitmask |= (1 << MipsRegisterInfo::
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getRegisterNumbering(RI.getRARegister()));
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// Print CPUBitmask
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O << "\t.mask \t"; printHex32(CPUBitmask); O << ','
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<< MipsFI->getCPUTopSavedRegOff() << '\n';
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// Print FPUBitmask
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O << "\t.fmask\t"; printHex32(FPUBitmask); O << ","
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<< MipsFI->getFPUTopSavedRegOff() << '\n';
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}
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// Print a 32 bit hex number with all numbers.
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void MipsAsmPrinter::
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printHex32(unsigned int Value)
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{
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O << "0x";
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for (int i = 7; i >= 0; i--)
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O << utohexstr( (Value & (0xF << (i*4))) >> (i*4) );
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}
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//===----------------------------------------------------------------------===//
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// Frame and Set directives
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//===----------------------------------------------------------------------===//
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/// Frame Directive
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void MipsAsmPrinter::
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emitFrameDirective(MachineFunction &MF)
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{
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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unsigned stackReg = RI.getFrameRegister(MF);
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unsigned returnReg = RI.getRARegister();
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unsigned stackSize = MF.getFrameInfo()->getStackSize();
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O << "\t.frame\t" << '$' << LowercaseString(RI.get(stackReg).AsmName)
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<< ',' << stackSize << ','
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<< '$' << LowercaseString(RI.get(returnReg).AsmName)
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<< '\n';
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}
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/// Emit Set directives.
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const char * MipsAsmPrinter::
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emitCurrentABIString(void)
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{
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switch(Subtarget->getTargetABI()) {
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case MipsSubtarget::O32: return "abi32";
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case MipsSubtarget::O64: return "abiO64";
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case MipsSubtarget::N32: return "abiN32";
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case MipsSubtarget::N64: return "abi64";
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case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
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default: break;
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}
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assert(0 && "Unknown Mips ABI");
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return NULL;
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}
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/// Emit the directives used by GAS on the start of functions
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void MipsAsmPrinter::
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emitFunctionStart(MachineFunction &MF)
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{
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// Print out the label for the function.
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const Function *F = MF.getFunction();
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SwitchToSection(TAI->SectionForGlobal(F));
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// 2 bits aligned
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EmitAlignment(2, F);
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O << "\t.globl\t" << CurrentFnName << '\n';
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O << "\t.ent\t" << CurrentFnName << '\n';
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printVisibility(CurrentFnName, F->getVisibility());
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if ((TAI->hasDotTypeDotSizeDirective()) && Subtarget->isLinux())
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O << "\t.type\t" << CurrentFnName << ", @function\n";
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O << CurrentFnName << ":\n";
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emitFrameDirective(MF);
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printSavedRegsBitmask(MF);
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O << '\n';
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}
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/// Emit the directives used by GAS on the end of functions
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void MipsAsmPrinter::
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emitFunctionEnd(MachineFunction &MF)
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{
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// There are instruction for this macros, but they must
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// always be at the function end, and we can't emit and
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// break with BB logic.
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O << "\t.set\tmacro\n";
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O << "\t.set\treorder\n";
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O << "\t.end\t" << CurrentFnName << '\n';
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if (TAI->hasDotTypeDotSizeDirective() && !Subtarget->isLinux())
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O << "\t.size\t" << CurrentFnName << ", .-" << CurrentFnName << '\n';
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}
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/// runOnMachineFunction - This uses the printMachineInstruction()
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/// method to print assembly for each instruction.
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bool MipsAsmPrinter::
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runOnMachineFunction(MachineFunction &MF)
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{
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this->MF = &MF;
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SetupMachineFunction(MF);
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// Print out constants referenced by the function
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EmitConstantPool(MF.getConstantPool());
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// Print out jump tables referenced by the function
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EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
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O << "\n\n";
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// Emit the function start directives
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emitFunctionStart(MF);
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// Print out code for the function.
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for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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// Print a label for the basic block.
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if (I != MF.begin()) {
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printBasicBlockLabel(I, true, true);
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O << '\n';
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}
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for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
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II != E; ++II) {
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// Print the assembly for the instruction.
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printInstruction(II);
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++EmittedInsts;
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}
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// Each Basic Block is separated by a newline
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O << '\n';
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}
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// Emit function end directives
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emitFunctionEnd(MF);
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// We didn't modify anything.
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return false;
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}
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// Print out an operand for an inline asm expression.
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bool MipsAsmPrinter::
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PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode)
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{
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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printOperand(MI, OpNo);
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return false;
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}
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void MipsAsmPrinter::
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printOperand(const MachineInstr *MI, int opNum)
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{
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const MachineOperand &MO = MI->getOperand(opNum);
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const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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bool closeP = false;
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bool isPIC = (TM.getRelocationModel() == Reloc::PIC_);
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bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
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// %hi and %lo used on mips gas to load global addresses on
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// static code. %got is used to load global addresses when
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// using PIC_. %call16 is used to load direct call targets
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// on PIC_ and small code size. %call_lo and %call_hi load
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// direct call targets on PIC_ and large code size.
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if (MI->getOpcode() == Mips::LUi && !MO.isReg() && !MO.isImm()) {
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if ((isPIC) && (isCodeLarge))
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O << "%call_hi(";
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else
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O << "%hi(";
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closeP = true;
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} else if ((MI->getOpcode() == Mips::ADDiu) && !MO.isReg() && !MO.isImm()) {
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const MachineOperand &firstMO = MI->getOperand(opNum-1);
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if (firstMO.getReg() == Mips::GP)
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O << "%gp_rel(";
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else
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O << "%lo(";
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closeP = true;
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} else if ((isPIC) && (MI->getOpcode() == Mips::LW) &&
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(!MO.isReg()) && (!MO.isImm())) {
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const MachineOperand &firstMO = MI->getOperand(opNum-1);
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const MachineOperand &lastMO = MI->getOperand(opNum+1);
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if ((firstMO.isReg()) && (lastMO.isReg())) {
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if ((firstMO.getReg() == Mips::T9) && (lastMO.getReg() == Mips::GP)
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&& (!isCodeLarge))
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O << "%call16(";
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else if ((firstMO.getReg() != Mips::T9) && (lastMO.getReg() == Mips::GP))
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O << "%got(";
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else if ((firstMO.getReg() == Mips::T9) && (lastMO.getReg() != Mips::GP)
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&& (isCodeLarge))
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O << "%call_lo(";
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closeP = true;
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}
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}
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switch (MO.getType())
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{
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case MachineOperand::MO_Register:
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if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
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O << '$' << LowercaseString (RI.get(MO.getReg()).AsmName);
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else
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O << '$' << MO.getReg();
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break;
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case MachineOperand::MO_Immediate:
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O << (short int)MO.getImm();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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printBasicBlockLabel(MO.getMBB());
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return;
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case MachineOperand::MO_GlobalAddress:
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{
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const GlobalValue *GV = MO.getGlobal();
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O << Mang->getValueName(GV);
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}
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break;
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case MachineOperand::MO_ExternalSymbol:
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O << MO.getSymbolName();
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break;
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case MachineOperand::MO_JumpTableIndex:
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O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
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<< '_' << MO.getIndex();
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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O << TAI->getPrivateGlobalPrefix() << "CPI"
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<< getFunctionNumber() << "_" << MO.getIndex();
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break;
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default:
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O << "<unknown operand type>"; abort (); break;
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}
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if (closeP) O << ")";
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}
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void MipsAsmPrinter::
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printUnsignedImm(const MachineInstr *MI, int opNum)
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{
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const MachineOperand &MO = MI->getOperand(opNum);
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if (MO.getType() == MachineOperand::MO_Immediate)
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O << (unsigned short int)MO.getImm();
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else
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printOperand(MI, opNum);
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}
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void MipsAsmPrinter::
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printMemOperand(const MachineInstr *MI, int opNum, const char *Modifier)
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{
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// when using stack locations for not load/store instructions
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// print the same way as all normal 3 operand instructions.
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if (Modifier && !strcmp(Modifier, "stackloc")) {
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printOperand(MI, opNum+1);
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O << ", ";
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printOperand(MI, opNum);
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return;
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}
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// Load/Store memory operands -- imm($reg)
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// If PIC target the target is loaded as the
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// pattern lw $25,%call16($28)
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printOperand(MI, opNum);
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O << "(";
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printOperand(MI, opNum+1);
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O << ")";
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}
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void MipsAsmPrinter::
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printFCCOperand(const MachineInstr *MI, int opNum, const char *Modifier)
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{
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const MachineOperand& MO = MI->getOperand(opNum);
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O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
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}
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bool MipsAsmPrinter::
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doInitialization(Module &M)
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{
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Mang = new Mangler(M, "", TAI->getPrivateGlobalPrefix());
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// Tell the assembler which ABI we are using
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O << "\t.section .mdebug." << emitCurrentABIString() << '\n';
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// TODO: handle O64 ABI
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if (Subtarget->isABI_EABI())
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O << "\t.section .gcc_compiled_long" <<
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(Subtarget->isGP32bit() ? "32" : "64") << '\n';
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// return to previous section
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O << "\t.previous" << '\n';
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return false; // success
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}
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void MipsAsmPrinter::
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printModuleLevelGV(const GlobalVariable* GVar) {
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const TargetData *TD = TM.getTargetData();
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if (!GVar->hasInitializer())
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return; // External global require no code
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// Check to see if this is a special global used by LLVM, if so, emit it.
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if (EmitSpecialLLVMGlobal(GVar))
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return;
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O << "\n\n";
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std::string name = Mang->getValueName(GVar);
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Constant *C = GVar->getInitializer();
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const Type *CTy = C->getType();
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|
unsigned Size = TD->getTypePaddedSize(CTy);
|
|
const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
|
|
bool printSizeAndType = true;
|
|
|
|
// A data structure or array is aligned in memory to the largest
|
|
// alignment boundary required by any data type inside it (this matches
|
|
// the Preferred Type Alignment). For integral types, the alignment is
|
|
// the type size.
|
|
unsigned Align;
|
|
if (CTy->getTypeID() == Type::IntegerTyID ||
|
|
CTy->getTypeID() == Type::VoidTyID) {
|
|
assert(!(Size & (Size-1)) && "Alignment is not a power of two!");
|
|
Align = Log2_32(Size);
|
|
} else
|
|
Align = TD->getPreferredTypeAlignmentShift(CTy);
|
|
|
|
printVisibility(name, GVar->getVisibility());
|
|
|
|
SwitchToSection(TAI->SectionForGlobal(GVar));
|
|
|
|
if (C->isNullValue() && !GVar->hasSection()) {
|
|
if (!GVar->isThreadLocal() &&
|
|
(GVar->hasLocalLinkage() || GVar->isWeakForLinker())) {
|
|
if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
|
|
|
|
if (GVar->hasLocalLinkage())
|
|
O << "\t.local\t" << name << '\n';
|
|
|
|
O << TAI->getCOMMDirective() << name << ',' << Size;
|
|
if (TAI->getCOMMDirectiveTakesAlignment())
|
|
O << ',' << (1 << Align);
|
|
|
|
O << '\n';
|
|
return;
|
|
}
|
|
}
|
|
switch (GVar->getLinkage()) {
|
|
case GlobalValue::LinkOnceAnyLinkage:
|
|
case GlobalValue::LinkOnceODRLinkage:
|
|
case GlobalValue::CommonAnyLinkage:
|
|
case GlobalValue::CommonODRLinkage:
|
|
case GlobalValue::WeakAnyLinkage:
|
|
case GlobalValue::WeakODRLinkage:
|
|
// FIXME: Verify correct for weak.
|
|
// Nonnull linkonce -> weak
|
|
O << "\t.weak " << name << '\n';
|
|
break;
|
|
case GlobalValue::AppendingLinkage:
|
|
// FIXME: appending linkage variables should go into a section of their name
|
|
// or something. For now, just emit them as external.
|
|
case GlobalValue::ExternalLinkage:
|
|
// If external or appending, declare as a global symbol
|
|
O << TAI->getGlobalDirective() << name << '\n';
|
|
// Fall Through
|
|
case GlobalValue::PrivateLinkage:
|
|
case GlobalValue::InternalLinkage:
|
|
if (CVA && CVA->isCString())
|
|
printSizeAndType = false;
|
|
break;
|
|
case GlobalValue::GhostLinkage:
|
|
cerr << "Should not have any unmaterialized functions!\n";
|
|
abort();
|
|
case GlobalValue::DLLImportLinkage:
|
|
cerr << "DLLImport linkage is not supported by this target!\n";
|
|
abort();
|
|
case GlobalValue::DLLExportLinkage:
|
|
cerr << "DLLExport linkage is not supported by this target!\n";
|
|
abort();
|
|
default:
|
|
assert(0 && "Unknown linkage type!");
|
|
}
|
|
|
|
EmitAlignment(Align, GVar);
|
|
|
|
if (TAI->hasDotTypeDotSizeDirective() && printSizeAndType) {
|
|
O << "\t.type " << name << ",@object\n";
|
|
O << "\t.size " << name << ',' << Size << '\n';
|
|
}
|
|
|
|
O << name << ":\n";
|
|
EmitGlobalConstant(C);
|
|
}
|
|
|
|
bool MipsAsmPrinter::
|
|
doFinalization(Module &M)
|
|
{
|
|
// Print out module-level global variables here.
|
|
for (Module::const_global_iterator I = M.global_begin(),
|
|
E = M.global_end(); I != E; ++I)
|
|
printModuleLevelGV(I);
|
|
|
|
O << '\n';
|
|
|
|
return AsmPrinter::doFinalization(M);
|
|
}
|