mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
174 lines
7.4 KiB
LLVM
174 lines
7.4 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
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%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
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%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
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%struct.__neon_int64x1x4_t = type { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> }
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%struct.__neon_int8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }
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%struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
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%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
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define <8 x i8> @vld4i8(i8* %A) nounwind {
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;CHECK-LABEL: vld4i8:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64]
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%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8)
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%tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
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%tmp4 = add <8 x i8> %tmp2, %tmp3
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ret <8 x i8> %tmp4
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}
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;Check for a post-increment updating load with register increment.
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define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
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;CHECK-LABEL: vld4i8_update:
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;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1
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%A = load i8*, i8** %ptr
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%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16)
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%tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
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%tmp4 = add <8 x i8> %tmp2, %tmp3
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%tmp5 = getelementptr i8, i8* %A, i32 %inc
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store i8* %tmp5, i8** %ptr
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vld4i16(i16* %A) nounwind {
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;CHECK-LABEL: vld4i16:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 16)
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%tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2
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%tmp4 = add <4 x i16> %tmp2, %tmp3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vld4i32(i32* %A) nounwind {
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;CHECK-LABEL: vld4i32:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256]
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 32)
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%tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2
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%tmp4 = add <2 x i32> %tmp2, %tmp3
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ret <2 x i32> %tmp4
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}
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define <2 x float> @vld4f(float* %A) nounwind {
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;CHECK-LABEL: vld4f:
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;CHECK: vld4.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 2
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%tmp4 = fadd <2 x float> %tmp2, %tmp3
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ret <2 x float> %tmp4
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}
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define <1 x i64> @vld4i64(i64* %A) nounwind {
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;CHECK-LABEL: vld4i64:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld1.64 {d16, d17, d18, d19}, [r0:256]
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64)
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%tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
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%tmp4 = add <1 x i64> %tmp2, %tmp3
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ret <1 x i64> %tmp4
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}
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define <1 x i64> @vld4i64_update(i64** %ptr, i64* %A) nounwind {
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;CHECK-LABEL: vld4i64_update:
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;CHECK: vld1.64 {d16, d17, d18, d19}, [r1:256]!
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64)
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%tmp5 = getelementptr i64, i64* %A, i32 4
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store i64* %tmp5, i64** %ptr
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%tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
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%tmp4 = add <1 x i64> %tmp2, %tmp3
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ret <1 x i64> %tmp4
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}
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define <16 x i8> @vld4Qi8(i8* %A) nounwind {
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;CHECK-LABEL: vld4Qi8:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]!
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;CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]
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%tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 64)
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%tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2
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%tmp4 = add <16 x i8> %tmp2, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vld4Qi16(i16* %A) nounwind {
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;CHECK-LABEL: vld4Qi16:
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;Check for no alignment specifier.
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;CHECK: vld4.16 {d16, d18, d20, d22}, [r0]!
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;CHECK: vld4.16 {d17, d19, d21, d23}, [r0]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2
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%tmp4 = add <8 x i16> %tmp2, %tmp3
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ret <8 x i16> %tmp4
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}
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;Check for a post-increment updating load.
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define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
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;CHECK-LABEL: vld4Qi16_update:
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;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]!
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;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]!
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%A = load i16*, i16** %ptr
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8)
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%tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2
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%tmp4 = add <8 x i16> %tmp2, %tmp3
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%tmp5 = getelementptr i16, i16* %A, i32 32
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store i16* %tmp5, i16** %ptr
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vld4Qi32(i32* %A) nounwind {
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;CHECK-LABEL: vld4Qi32:
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;CHECK: vld4.32
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;CHECK: vld4.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 2
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%tmp4 = add <4 x i32> %tmp2, %tmp3
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ret <4 x i32> %tmp4
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}
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define <4 x float> @vld4Qf(float* %A) nounwind {
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;CHECK-LABEL: vld4Qf:
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;CHECK: vld4.32
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;CHECK: vld4.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8* %tmp0, i32 1)
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%tmp2 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 2
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%tmp4 = fadd <4 x float> %tmp2, %tmp3
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ret <4 x float> %tmp4
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}
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declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8*, i32) nounwind readonly
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declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8*, i32) nounwind readonly
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declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8*, i32) nounwind readonly
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declare %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8*, i32) nounwind readonly
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declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8*, i32) nounwind readonly
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declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8*, i32) nounwind readonly
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declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i8*, i32) nounwind readonly
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declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8*, i32) nounwind readonly
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