Jiangning Liu 66b123f0d8 [ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out argument stack from callee. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208837 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-15 01:33:17 +00:00
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AArch64	[ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out argument stack from callee.	2014-05-15 01:33:17 +00:00
ARM	Rename ComputeMaskedBits to computeKnownBits. "Masked" has been	2014-05-14 21:14:37 +00:00
ARM64	[ARM64-BE] Fix byte order of CIE and FDE frames for exception handling	2014-05-14 16:51:58 +00:00
CPP
Generic
Hexagon	DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.	2014-05-14 21:52:46 +00:00
Inputs
Mips	Allow sret on the second parameter as well as the first	2014-05-09 22:32:13 +00:00
MSP430
NVPTX
PowerPC	DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.	2014-05-14 21:52:46 +00:00
R600	Rename ComputeMaskedBits to computeKnownBits. "Masked" has been	2014-05-14 21:14:37 +00:00
SPARC	Allow sret on the second parameter as well as the first	2014-05-09 22:32:13 +00:00
SystemZ
Thumb
Thumb2
X86	Rename ComputeMaskedBits to computeKnownBits. "Masked" has been	2014-05-14 21:14:37 +00:00
XCore